From 285a8728d3731cc43560679723cdf380fbc0bfa5 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 9 Jan 2021 15:05:24 +0000 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index e48898173..59d0e8b13 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -118,11 +118,40 @@ an alternative table meaning for [[sv/svp64]] mode. TODO + in all cases: + - vector immed(RA) nonsense. + - unit-stride/el-stride needed on immed(RA) + + modes for immed(RA) version: + + * saturation + * predicate-result? + * normal + * fail-first + - vector RA is "banned" + +| 0-1 | 2 | 3 4 | description | +| --- | --- |---------|-------------------------- | +| 00 | 0 | sz dz | normal mode | +| 01 | inv | CR-bit | Rc=1: ffirst CR sel | +| 01 | inv | sz RC1 | Rc=0: ffirst z/nonz | +| 10 | N | sz dz | sat mode: N=0/1 u/s | +| 11 | inv | CR-bit | Rc=1: pred-result CR sel | +| 11 | inv | sz RC1 | Rc=0: pred-result z/nonz | + + + modes for RA+RB indexed version: + + * saturation + * predicate-result + * normal + * fail-first + - vector RA or RB is "banned" + + | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | | 00 | 0 | sz dz | normal mode | -| 00 | 1 | sz CRM | reduce mode (mapreduce), SUBVL=1 | -| 00 | 1 | SVM CRM | subvector reduce mode, SUBVL>1 | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | sz RC1 | Rc=0: ffirst z/nonz | | 10 | N | sz dz | sat mode: N=0/1 u/s | -- 2.30.2