From 28638852cc74861c4fb5095aa1e712f26b3f364a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Sep 2020 22:44:56 +0100 Subject: [PATCH] change litex sdram pinouts to ASIC type --- src/soc/litex/florent/libresoc/ls180.py | 10 ++- src/soc/litex/florent/ls180pins.txt | 60 ++++++++-------- src/soc/litex/florent/ls180soc.py | 93 +++++++++++++++++++++---- 3 files changed, 119 insertions(+), 44 deletions(-) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index 7a04ba5b..e3969641 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -94,13 +94,19 @@ _io = [ Subsignal("a", Pins( "M20 M19 L20 L19 K20 K19 K18 J20", "J19 H20 N19 G20 G19 E14 E15 E16")), - Subsignal("dq", Pins( + Subsignal("dq_i", Pins( + "J16 L18 M18 N18 P18 T18 T17 U20", + "E19 D20 D19 C20 E18 F18 J18 J17")), + Subsignal("dq_o", Pins( + "J16 L18 M18 N18 P18 T18 T17 U20", + "E19 D20 D19 C20 E18 F18 J18 J17")), + Subsignal("dq_oe", Pins( "J16 L18 M18 N18 P18 T18 T17 U20", "E19 D20 D19 C20 E18 F18 J18 J17")), Subsignal("we_n", Pins("T20")), Subsignal("ras_n", Pins("R20")), Subsignal("cas_n", Pins("T19")), - Subsignal("cs_n", Pins("P20")), + Subsignal("cs_n", Pins("P20 P30 P31 P32")), Subsignal("cke", Pins("F20")), Subsignal("ba", Pins("P19 N20")), Subsignal("dm", Pins("U19 E20")), diff --git a/src/soc/litex/florent/ls180pins.txt b/src/soc/litex/florent/ls180pins.txt index f6e57de6..650b3629 100644 --- a/src/soc/litex/florent/ls180pins.txt +++ b/src/soc/litex/florent/ls180pins.txt @@ -8,8 +8,8 @@ N6 | JTAG0 tdi N7 | JTAG0 tdo N8 | UART0 tx N9 | UART0 rx -N10 | GPIOOUT0 gpio0 -N11 | GPIOIN0 gpio0 +N10 | GPIO0 gpio0 +N11 | GPIO0 gpio1 N12 | VDD N13 | SPI0 clk N14 | SPI0 mosi @@ -23,11 +23,11 @@ N21 | SDCARD0 data1 N22 | SDCARD0 data2 N23 | SDCARD0 data3 N24 | VDD -N25 | nc -N26 | nc -N27 | VDD -N28 | nc -N29 | nc +N25 | SDRAM0 cs0_n +N26 | SDRAM0 cs1_n +N27 | SDRAM0 cs2_n +N28 | SDRAM0 cs3_n +N29 | VDD N30 | nc N31 | VSS @@ -55,16 +55,16 @@ E20 | VSS E21 | SDRAM0 we_n E22 | SDRAM0 ras_n E23 | SDRAM0 cas_n -E24 | SDRAM0 cs_n -E25 | SDRAM0 cke -E26 | VDD -E27 | SDRAM0 ba0 -E28 | SDRAM0 ba1 -E29 | SDRAM0 dm0 -E30 | SDRAM0 dm1 -E31 | VSS +E24 | SDRAM0 cke +E25 | VDD +E26 | SDRAM0 ba0 +E27 | SDRAM0 ba1 +E28 | SDRAM0 dm0 +E29 | SDRAM0 dm1 +E30 | VSS +E31 | SDRAM0 sdram_clock -S0 | SDRAM0 sdram_clock +S0 | nc S1 | VDD S2 | SDRAM0 dq0 S3 | SDRAM0 dq1 @@ -88,8 +88,8 @@ S20 | PWM0 pwm0 S21 | PWM1 pwm1 S22 | VSS S23 | EINT0 eint0 -S24 | GPIOOUT0 gpio1 -S25 | GPIOIN0 gpio1 +S24 | GPIO0 gpio14 +S25 | GPIO0 gpio15 S26 | nc S27 | nc S28 | nc @@ -105,18 +105,18 @@ W4 | SPI1 miso W5 | VDD W6 | UART1 tx W7 | UART1 rx -W8 | GPIOOUT0 gpio2 -W9 | GPIOOUT0 gpio3 -W10 | GPIOOUT0 gpio4 -W11 | GPIOOUT0 gpio5 -W12 | GPIOOUT0 gpio6 -W13 | GPIOOUT0 gpio7 -W14 | GPIOIN0 gpio2 -W15 | GPIOIN0 gpio3 -W16 | GPIOIN0 gpio4 -W17 | GPIOIN0 gpio5 -W18 | GPIOIN0 gpio6 -W19 | GPIOIN0 gpio7 +W8 | GPIO0 gpio2 +W9 | GPIO0 gpio3 +W10 | GPIO0 gpio4 +W11 | GPIO0 gpio5 +W12 | GPIO0 gpio6 +W13 | GPIO0 gpio7 +W14 | GPIO0 gpio8 +W15 | GPIO0 gpio9 +W16 | GPIO0 gpio10 +W17 | GPIO0 gpio11 +W18 | GPIO0 gpio12 +W19 | GPIO0 gpio13 W20 | VSS W21 | EINT0 eint1 W22 | EINT0 eint2 diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 6f3a559e..61f18b8a 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -6,7 +6,7 @@ from functools import reduce from operator import or_ from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState, - Record, ClockSignal, wrap) + Cat, Record, ClockSignal, wrap) from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform @@ -21,8 +21,9 @@ from litex.soc.integration.common import get_mem_data from litedram import modules as litedram_modules from litedram.phy.model import SDRAMPHYModel -from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY - +#from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY +from litedram.common import PHYPadsCombiner, PhySettings +from litedram.phy.dfi import Interface as DFIInterface from litex.soc.cores.spi import SPIMaster from litex.soc.cores.pwm import PWM from litex.soc.cores.bitbang import I2CMaster @@ -83,15 +84,15 @@ class GPIOTristateASIC(Module, AutoCSR): # SDCard PHY IO ------------------------------------------------------- class SDRPad(Module): - def __init__(self, pad, name, sdpad): + def __init__(self, pad, name, o, oe, i): clk = ClockSignal() _o = getattr(pad, "%s_o" % name) _oe = getattr(pad, "%s_oe" % name) _i = getattr(pad, "%s_i" % name) for j in range(len(_o)): - self.specials += SDROutput(clk=clk, i=sdpad.o[j], o=_o[j]) - self.specials += SDROutput(clk=clk, i=sdpad.oe, o=_oe[j]) - self.specials += SDRInput(clk=clk, i=_i[j], o=sdpad.i[j]) + self.specials += SDROutput(clk=clk, i=o[j], o=_o[j]) + self.specials += SDROutput(clk=clk, i=oe, o=_oe[j]) + self.specials += SDRInput(clk=clk, i=_i[j], o=i[j]) class SDPHYIOGen(Module): @@ -108,10 +109,12 @@ class SDPHYIOGen(Module): ) # Cmd - self.submodules.sd_cmd = SDRPad(pads, "cmd", sdpads.cmd) + c = sdpads.cmd + self.submodules.sd_cmd = SDRPad(pads, "cmd", c.o, c.oe, c.i) # Data - self.submodules.sd_data = SDRPad(pads, "data", sdpads.data) + d = sdpads.data + self.submodules.sd_data = SDRPad(pads, "data", d.o, d.oe, d.i) class SDPHY(Module, AutoCSR): @@ -155,11 +158,77 @@ class SDPHY(Module, AutoCSR): self.comb += m.pads_in.cmd.i.eq(sdpads.cmd.i) self.comb += m.pads_in.data.i.eq(sdpads.data.i) - # Speed Throttling ------------------------------------------- self.comb += clocker.stop.eq(dataw.stop | datar.stop) -# LibreSoCSim ----------------------------------------------------------- + +# Generic SDR PHY --------------------------------------------------------- + +class GENSDRPHY(Module): + def __init__(self, pads, cl=2, cmd_latency=1): + pads = PHYPadsCombiner(pads) + addressbits = len(pads.a) + bankbits = len(pads.ba) + nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n) + databits = len(pads.dq_i) + assert cl in [2, 3] + assert databits%8 == 0 + + # PHY settings ---------------------------------------------------- + self.settings = PhySettings( + phytype = "GENSDRPHY", + memtype = "SDR", + databits = databits, + dfi_databits = databits, + nranks = nranks, + nphases = 1, + rdphase = 0, + wrphase = 0, + rdcmdphase = 0, + wrcmdphase = 0, + cl = cl, + read_latency = cl + cmd_latency, + write_latency = 0 + ) + + # DFI Interface --------------------------------------------------- + self.dfi = dfi = DFIInterface(addressbits, bankbits, nranks, databits) + + # # # + + # Iterate on pads groups ------------------------------------------ + for pads_group in range(len(pads.groups)): + pads.sel_group(pads_group) + + # Addresses and Commands -------------------------------------- + self.specials += [SDROutput(i=dfi.p0.address[i], o=pads.a[i]) + for i in range(len(pads.a))] + self.specials += [SDROutput(i=dfi.p0.bank[i], o=pads.ba[i]) + for i in range(len(pads.ba))] + self.specials += SDROutput(i=dfi.p0.cas_n, o=pads.cas_n) + self.specials += SDROutput(i=dfi.p0.ras_n, o=pads.ras_n) + self.specials += SDROutput(i=dfi.p0.we_n, o=pads.we_n) + if hasattr(pads, "cke"): + self.specials += SDROutput(i=dfi.p0.cke, o=pads.cke) + if hasattr(pads, "cs_n"): + self.specials += SDROutput(i=dfi.p0.cs_n, o=pads.cs_n) + + # DQ/DM Data Path ------------------------------------------------- + + d = dfi.p0 + self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata) + + if hasattr(pads, "dm"): + for i in range(len(pads.dm)): + self.comb += pads.dm[i].eq(0) # FIXME + + # DQ/DM Control Path ---------------------------------------------- + rddata_en = Signal(cl + cmd_latency) + self.sync += rddata_en.eq(Cat(dfi.p0.rddata_en, rddata_en)) + self.sync += dfi.p0.rddata_valid.eq(rddata_en[-1]) + + +# LibreSoC 180nm ASIC ------------------------------------------------------- class LibreSoCSim(SoCCore): def __init__(self, cpu="libresoc", debug=False, with_sdram=True, @@ -275,7 +344,7 @@ class LibreSoCSim(SoCCore): phy = self.sdrphy, module = sdram_module, origin = self.mem_map["main_ram"], - size = 0x40000000, + size = 0x80000000, l2_cache_size = 0, # 8192 l2_cache_min_data_width = 128, l2_cache_reverse = True -- 2.30.2