From 28a12c2cb1809dad949f42bb194dc2d627c8ec93 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Sep 2020 16:38:56 +0100 Subject: [PATCH] whoops, ICS in litex sim needs to be 0x1000 size region --- src/soc/litex/florent/sim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index a2125900..dcae6fbf 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -114,12 +114,12 @@ class LibreSoCSim(SoCSDRAM): # XICS interrupt devices icp_addr = self.mem_map['icp'] icp_wb = self.cpu.xics_icp - icp_region = SoCRegion(origin=icp_addr, size=0x1000, cached=False) + icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False) self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region) ics_addr = self.mem_map['ics'] ics_wb = self.cpu.xics_ics - ics_region = SoCRegion(origin=ics_addr, size=0x20, cached=False) + ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False) self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region) # Simple GPIO peripheral -- 2.30.2