From 28a1332274d6e03aebcf182729cd608c06a24d75 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 30 Jan 2021 13:17:45 +0000 Subject: [PATCH] extend CR registers in Decode2ToExecute1Type to 7 bit --- src/soc/decoder/decode2execute1.py | 8 ++++---- src/soc/decoder/power_decoder2.py | 16 +++++++++++----- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index 75b66d36..a6ac6262 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -109,10 +109,10 @@ class Decode2ToExecute1Type(RecordObject): self.write_fast1 = Data(3, name="fasto1") self.write_fast2 = Data(3, name="fasto2") - self.read_cr1 = Data(3, name="cr_in1") - self.read_cr2 = Data(3, name="cr_in2") - self.read_cr3 = Data(3, name="cr_in2") - self.write_cr = Data(3, name="cr_out") + self.read_cr1 = Data(7, name="cr_in1") + self.read_cr2 = Data(7, name="cr_in2") + self.read_cr3 = Data(7, name="cr_in2") + self.write_cr = Data(7, name="cr_out") # decode operand data print ("decode2execute init", name, opkls, do) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index c3ef17f6..abad1291 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -100,7 +100,7 @@ class SVP64ExtraSpec(Elaboratable): # back in the LDSTRM-* and RM-* files generated by sv_analysis.py # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain - # the register-extension information. extract those how + # the register-extension information. extract those now with m.Switch(self.etype): # 2-bit index selection mode with m.Case(SVEtype.EXTRA2): @@ -729,6 +729,9 @@ class DecodeCRIn(Elaboratable): comb = m.d.comb op = self.dec.op + m.submodules.svdec = svdec = SVP64CRExtra() + m.submodules.svdec_b = svdec_b = SVP64CRExtra() + m.submodules.svdec_o = svdec_o = SVP64CRExtra() comb += self.cr_bitfield.ok.eq(0) comb += self.cr_bitfield_b.ok.eq(0) @@ -1133,10 +1136,13 @@ class PowerDecode2(PowerDecodeSubset): comb += e.write_fast2.eq(dec_o2.fast_out) # condition registers (CR) - comb += e.read_cr1.eq(self.dec_cr_in.cr_bitfield) - comb += e.read_cr2.eq(self.dec_cr_in.cr_bitfield_b) - comb += e.read_cr3.eq(self.dec_cr_in.cr_bitfield_o) - comb += e.write_cr.eq(self.dec_cr_out.cr_bitfield) + for to_reg, fromreg in ( + (e.read_cr1, self.dec_cr_in.cr_bitfield), + (e.read_cr2, self.dec_cr_in.cr_bitfield_b), + (e.read_cr3, self.dec_cr_in.cr_bitfield_o), + (e.write_cr, self.dec_cr_out.cr_bitfield)): + comb += to_reg.data.eq(fromreg.data) + comb += to_reg.ok.eq(fromreg.ok) # sigh this is exactly the sort of thing for which the # decoder is designed to not need. MTSPR, MFSPR and others need -- 2.30.2