From 28a2f9235c40f67717827308c99db8dac50652c6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 18 Mar 2022 12:45:41 +0000 Subject: [PATCH] rename TestHyperRAMPHY to just HyperRAMPHY --- lambdasoc/periph/hyperram.py | 2 +- lambdasoc/test/test_hyperbus.py | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index 626043c..36c72e9 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -96,7 +96,7 @@ class HyperRAMPads: self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)]) -class TestHyperRAMPHY(Elaboratable): +class HyperRAMPHY(Elaboratable): def __init__(self, pads): self.pads = pads self.clk = pads.clk diff --git a/lambdasoc/test/test_hyperbus.py b/lambdasoc/test/test_hyperbus.py index 3526bfc..41f2c54 100644 --- a/lambdasoc/test/test_hyperbus.py +++ b/lambdasoc/test/test_hyperbus.py @@ -13,7 +13,7 @@ import unittest from nmigen import (Record, Module, Signal, Elaboratable) from nmigen.compat.sim import run_simulation -from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, TestHyperRAMPHY +from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, HyperRAMPHY def c2bool(c): return {"-": 1, "_": 0}[c] @@ -95,7 +95,7 @@ class TestHyperBusWrite(unittest.TestCase): (yield dut.phy.pads.rwds.o)) yield - dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY) + dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY) run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") @@ -133,7 +133,7 @@ class TestHyperBusWrite(unittest.TestCase): (yield dut.phy.pads.rwds.oe)) yield - dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY) + dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY) run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="rd_sim.vcd") @@ -180,7 +180,7 @@ class TestHyperBusRead(unittest.TestCase): (yield dut.phy.pads.rwds.oe)) yield - dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY) + dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY) run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="rd_sim.vcd") -- 2.30.2