From 28a5550677ae09ce8d4f8b9df5cdd369b0c6499e Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 16:00:19 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index d8d4886e6..3cf0c5013 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -20,15 +20,18 @@ Links: # Introduction -This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section. -It is also crucial to note that whilst this format augments instruction -behaviour it works in conjunction with SVSTATE and other [[sv/sprs]]. - -Except where explicitly stated all bit numbers remain as in the Power ISA: +Simple-V is a type of Vectorisation best described as a "Prefix Loop Subsystem" +similar to the Z80 `LDIR` instruction and to the x86 `REP` Prefix instruction. +More advanced features are similar to the Z80 `CPIR` instruction. If viewed +as an actual Vector ISA it introduces over 1.5 million 64-bit Vector instructions. +SVP64, the instruction format, is therefore best viewed as an orthogonal +RISC-style "Prefixing" subsystem instead. + +Except where explicitly stated all bit numbers remain as in the rest of the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on the left and counting up as you move rightwards to the LSB end). All bit ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order). **All register numbering and -element numbering however is LSB0 ordering** which is a different convention used +element numbering however is LSB0 ordering** which is a different convention from that used elsewhere in the Power ISA. 64-bit instructions are split into two 32-bit words, the prefix and the @@ -36,7 +39,7 @@ suffix. The prefix always comes before the suffix in PC order. | 0:5 | 6:31 | 32:63 | |--------|--------------|--------------| -| EXT01 | v3.1 Prefix | v3.0/1 Suffix | +| EXT09 | v3.1 Prefix | v3.0/1 Suffix | svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict. -- 2.30.2