From 28afbcdf7fcc71c68d8410fbb6e9a85266d746d3 Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 19 Sep 2023 16:42:48 +0100
Subject: [PATCH] Added english description for lhzu instruction

---
 openpower/isa/fixedload.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 500489b7..0e2b6536 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -152,6 +152,10 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:Let the effective address (EA) be the sum
+(RA|0)+ (RB). The halfword in storage addressed by
+EA is loaded into RT 48:63. RT 0:47 are set to 0.
+
 Special Registers Altered:
 
     None
-- 
2.30.2