From 28dc3f6199e72af815d214b40f8b56cde5c6bdfa Mon Sep 17 00:00:00 2001 From: Topi Pohjolainen Date: Wed, 8 Jun 2016 20:51:32 +0300 Subject: [PATCH] i965: Move fast clear state enumeration into resolve map Status is still tracked per miptree. Next patch will switch to resolve map per slice/level. Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 58 ---------------- src/mesa/drivers/dri/i965/intel_resolve_map.c | 6 +- src/mesa/drivers/dri/i965/intel_resolve_map.h | 69 +++++++++++++++++-- 3 files changed, 68 insertions(+), 65 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index a6652693116..02f131c7316 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -201,64 +201,6 @@ enum intel_msaa_layout INTEL_MSAA_LAYOUT_CMS, }; - -/** - * Enum for keeping track of the fast clear state of a buffer associated with - * a miptree. - * - * Fast clear works by deferring the memory writes that would be used to clear - * the buffer, so that instead of performing them at the time of the clear - * operation, the hardware automatically performs them at the time that the - * buffer is later accessed for rendering. The MCS buffer keeps track of - * which regions of the buffer still have pending clear writes. - * - * This enum keeps track of the driver's knowledge of pending fast clears in - * the MCS buffer. - * - * MCS buffers only exist on Gen7+. - */ -enum intel_fast_clear_state -{ - /** - * No deferred clears are pending for this miptree, and the contents of the - * color buffer are entirely correct. An MCS buffer may or may not exist - * for this miptree. If it does exist, it is entirely in the "no deferred - * clears pending" state. If it does not exist, it will be created the - * first time a fast color clear is executed. - * - * In this state, the color buffer can be used for purposes other than - * rendering without needing a render target resolve. - * - * Since there is no such thing as a "fast color clear resolve" for MSAA - * buffers, an MSAA buffer will never be in this state. - */ - INTEL_FAST_CLEAR_STATE_RESOLVED, - - /** - * An MCS buffer exists for this miptree, and deferred clears are pending - * for some regions of the color buffer, as indicated by the MCS buffer. - * The contents of the color buffer are only correct for the regions where - * the MCS buffer doesn't indicate a deferred clear. - * - * If a single-sample buffer is in this state, a render target resolve must - * be performed before it can be used for purposes other than rendering. - */ - INTEL_FAST_CLEAR_STATE_UNRESOLVED, - - /** - * An MCS buffer exists for this miptree, and deferred clears are pending - * for the entire color buffer, and the contents of the MCS buffer reflect - * this. The contents of the color buffer are undefined. - * - * If a single-sample buffer is in this state, a render target resolve must - * be performed before it can be used for purposes other than rendering. - * - * If the client attempts to clear a buffer which is already in this state, - * the clear can be safely skipped, since the buffer is already clear. - */ - INTEL_FAST_CLEAR_STATE_CLEAR, -}; - enum miptree_array_layout { /* Each array slice contains all miplevels packed together. * diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.c b/src/mesa/drivers/dri/i965/intel_resolve_map.c index 56fd9547788..5b132caf194 100644 --- a/src/mesa/drivers/dri/i965/intel_resolve_map.c +++ b/src/mesa/drivers/dri/i965/intel_resolve_map.c @@ -33,9 +33,9 @@ */ void intel_resolve_map_set(struct exec_list *resolve_map, - uint32_t level, - uint32_t layer, - enum blorp_hiz_op need) + uint32_t level, + uint32_t layer, + unsigned need) { foreach_list_typed(struct intel_resolve_map, map, link, resolve_map) { if (map->level == level && map->layer == layer) { diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.h b/src/mesa/drivers/dri/i965/intel_resolve_map.h index 29cad8f4b6d..397860c4d9a 100644 --- a/src/mesa/drivers/dri/i965/intel_resolve_map.h +++ b/src/mesa/drivers/dri/i965/intel_resolve_map.h @@ -31,6 +31,63 @@ extern "C" { #endif +/** + * Enum for keeping track of the fast clear state of a buffer associated with + * a miptree. + * + * Fast clear works by deferring the memory writes that would be used to clear + * the buffer, so that instead of performing them at the time of the clear + * operation, the hardware automatically performs them at the time that the + * buffer is later accessed for rendering. The MCS buffer keeps track of + * which regions of the buffer still have pending clear writes. + * + * This enum keeps track of the driver's knowledge of pending fast clears in + * the MCS buffer. + * + * MCS buffers only exist on Gen7+. + */ +enum intel_fast_clear_state +{ + /** + * No deferred clears are pending for this miptree, and the contents of the + * color buffer are entirely correct. An MCS buffer may or may not exist + * for this miptree. If it does exist, it is entirely in the "no deferred + * clears pending" state. If it does not exist, it will be created the + * first time a fast color clear is executed. + * + * In this state, the color buffer can be used for purposes other than + * rendering without needing a render target resolve. + * + * Since there is no such thing as a "fast color clear resolve" for MSAA + * buffers, an MSAA buffer will never be in this state. + */ + INTEL_FAST_CLEAR_STATE_RESOLVED, + + /** + * An MCS buffer exists for this miptree, and deferred clears are pending + * for some regions of the color buffer, as indicated by the MCS buffer. + * The contents of the color buffer are only correct for the regions where + * the MCS buffer doesn't indicate a deferred clear. + * + * If a single-sample buffer is in this state, a render target resolve must + * be performed before it can be used for purposes other than rendering. + */ + INTEL_FAST_CLEAR_STATE_UNRESOLVED, + + /** + * An MCS buffer exists for this miptree, and deferred clears are pending + * for the entire color buffer, and the contents of the MCS buffer reflect + * this. The contents of the color buffer are undefined. + * + * If a single-sample buffer is in this state, a render target resolve must + * be performed before it can be used for purposes other than rendering. + * + * If the client attempts to clear a buffer which is already in this state, + * the clear can be safely skipped, since the buffer is already clear. + */ + INTEL_FAST_CLEAR_STATE_CLEAR, +}; + /** * \brief Map of miptree slices to needed resolves. * @@ -62,14 +119,18 @@ struct intel_resolve_map { uint32_t level; uint32_t layer; - enum blorp_hiz_op need; + + union { + enum blorp_hiz_op need; + enum intel_fast_clear_state fast_clear_state; + }; }; void intel_resolve_map_set(struct exec_list *resolve_map, - uint32_t level, - uint32_t layer, - enum blorp_hiz_op need); + uint32_t level, + uint32_t layer, + unsigned new_state); const struct intel_resolve_map * intel_resolve_map_find_any(const struct exec_list *resolve_map, -- 2.30.2