From 28dd61b782453624f0d10e6ace73b5e20506a4a6 Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Mon, 9 Dec 2019 14:49:08 +0000 Subject: [PATCH] Fix more unrecognised GCN instructions 2019-12-09 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (gather_insn_1offset): Change %s to %o in asm output. (gather_insn_2offsets): Likewise. From-SVN: r279131 --- gcc/ChangeLog | 6 ++++++ gcc/config/gcn/gcn-valu.md | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aec9bba15e7..82a1bfb6ef2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-12-09 Andrew Stubbs + + * config/gcn/gcn-valu.md (gather_insn_1offset): Change + %s to %o in asm output. + (gather_insn_2offsets): Likewise. + 2019-12-09 Richard Earnshaw * config/arm/t-multilib: Use arm->thumb multilib reuse rules diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 95e0731a374..16b37e8daab 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -722,7 +722,7 @@ sprintf (buf, "flat_load%%o0\t%%0, %%1%s\;s_waitcnt\t0", glc); } else if (AS_GLOBAL_P (as)) - sprintf (buf, "global_load%%s0\t%%0, %%1, off offset:%%2%s\;" + sprintf (buf, "global_load%%o0\t%%0, %%1, off offset:%%2%s\;" "s_waitcnt\tvmcnt(0)", glc); else gcc_unreachable (); @@ -780,7 +780,7 @@ /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[2]) - FIRST_VGPR_REG; - sprintf (buf, "global_load%%s0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" + sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); } else -- 2.30.2