From 28ddd87e570d35db09c4fe052c313d595de9d220 Mon Sep 17 00:00:00 2001 From: Fred Fish Date: Tue, 11 Feb 1997 22:04:35 +0000 Subject: [PATCH] * gas/tic80/{add.d, add.lst, add.s, bitnum.d, bitnum.lst, bitnum.s, ccode.d, ccode.lst, ccode.s, cregops.d, cregops.lst, cregops.s, endmask.d, endmask.lst, endmask.s, regops.d, regops.lst, regops.s, tic80.exp}: New files for TIc80 test cases. --- gas/testsuite/.Sanitize | 28 +++ gas/testsuite/ChangeLog | 9 + gas/testsuite/gas/tic80/.Sanitize | 51 ++++++ gas/testsuite/gas/tic80/add.d | 30 ++++ gas/testsuite/gas/tic80/add.lst | 34 ++++ gas/testsuite/gas/tic80/add.s | 19 ++ gas/testsuite/gas/tic80/bitnum.d | 38 ++++ gas/testsuite/gas/tic80/bitnum.lst | 44 +++++ gas/testsuite/gas/tic80/bitnum.s | 37 ++++ gas/testsuite/gas/tic80/ccode.d | 32 ++++ gas/testsuite/gas/tic80/ccode.lst | 37 ++++ gas/testsuite/gas/tic80/ccode.s | 30 ++++ gas/testsuite/gas/tic80/cregops.d | 68 +++++++ gas/testsuite/gas/tic80/cregops.lst | 76 ++++++++ gas/testsuite/gas/tic80/cregops.s | 64 +++++++ gas/testsuite/gas/tic80/endmask.d | 41 +++++ gas/testsuite/gas/tic80/endmask.lst | 45 +++++ gas/testsuite/gas/tic80/endmask.s | 38 ++++ gas/testsuite/gas/tic80/regops.d | 188 ++++++++++++++++++++ gas/testsuite/gas/tic80/regops.lst | 264 ++++++++++++++++++++++++++++ gas/testsuite/gas/tic80/regops.s | 237 +++++++++++++++++++++++++ gas/testsuite/gas/tic80/tic80.exp | 12 ++ 22 files changed, 1422 insertions(+) create mode 100644 gas/testsuite/gas/tic80/.Sanitize create mode 100644 gas/testsuite/gas/tic80/add.d create mode 100644 gas/testsuite/gas/tic80/add.lst create mode 100644 gas/testsuite/gas/tic80/add.s create mode 100644 gas/testsuite/gas/tic80/bitnum.d create mode 100644 gas/testsuite/gas/tic80/bitnum.lst create mode 100644 gas/testsuite/gas/tic80/bitnum.s create mode 100644 gas/testsuite/gas/tic80/ccode.d create mode 100644 gas/testsuite/gas/tic80/ccode.lst create mode 100644 gas/testsuite/gas/tic80/ccode.s create mode 100644 gas/testsuite/gas/tic80/cregops.d create mode 100644 gas/testsuite/gas/tic80/cregops.lst create mode 100644 gas/testsuite/gas/tic80/cregops.s create mode 100644 gas/testsuite/gas/tic80/endmask.d create mode 100644 gas/testsuite/gas/tic80/endmask.lst create mode 100644 gas/testsuite/gas/tic80/endmask.s create mode 100644 gas/testsuite/gas/tic80/regops.d create mode 100644 gas/testsuite/gas/tic80/regops.lst create mode 100644 gas/testsuite/gas/tic80/regops.s create mode 100644 gas/testsuite/gas/tic80/tic80.exp diff --git a/gas/testsuite/.Sanitize b/gas/testsuite/.Sanitize index baefb9f3d19..ccaf1a0e8e4 100644 --- a/gas/testsuite/.Sanitize +++ b/gas/testsuite/.Sanitize @@ -104,4 +104,32 @@ else done fi +tic80_files="ChangeLog" +if ( echo $* | grep keep\-tic80 > /dev/null ) ; then + for i in $tic80_files ; do + if test ! -d $i && (grep sanitize-tic80 $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Keeping tic80 stuff in $i + fi + fi + done +else + for i in $tic80_files ; do + if test ! -d $i && (grep sanitize-tic80 $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Removing traces of \"tic80\" from $i... + fi + cp $i new + sed '/start\-sanitize\-tic80/,/end-\sanitize\-tic80/d' < $i > new + if [ -n "${safe}" -a ! -f .Recover/$i ] ; then + if [ -n "${verbose}" ] ; then + echo Caching $i in .Recover... + fi + mv $i .Recover + fi + mv new $i + fi + done +fi + # End of file. diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 5636b2c1955..ba7e5ac3583 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,12 @@ +start-sanitize-tic80 +Tue Feb 11 14:45:39 1997 Fred Fish + + * gas/tic80/{add.d, add.lst, add.s, bitnum.d, bitnum.lst, bitnum.s, + ccode.d, ccode.lst, ccode.s, cregops.d, cregops.lst, cregops.s, + endmask.d, endmask.lst, endmask.s, regops.d, regops.lst, regops.s, + tic80.exp}: New files for TIc80 test cases. + +end-sanitize-tic80 Tue Feb 11 15:46:27 1997 Ian Lance Taylor * gas/mips/mips16.d: Update for change in disassembly output. diff --git a/gas/testsuite/gas/tic80/.Sanitize b/gas/testsuite/gas/tic80/.Sanitize new file mode 100644 index 00000000000..6f485ef881b --- /dev/null +++ b/gas/testsuite/gas/tic80/.Sanitize @@ -0,0 +1,51 @@ +# .Sanitize for devo/gas/testsuite/gas/tic80. + +# Each directory to survive it's way into a release will need a file +# like this one called "./.Sanitize". All keyword lines must exist, +# and must exist in the order specified by this file. Each directory +# in the tree will be processed, top down, in the following order. + +# Hash started lines like this one are comments and will be deleted +# before anything else is done. Blank lines will also be squashed +# out. + +# The lines between the "Do-first:" line and the "Things-to-keep:" +# line are executed as a /bin/sh shell script before anything else is +# done in this + +Do-first: + + +# All files listed between the "Things-to-keep:" line and the +# "Files-to-sed:" line will be kept. All other files will be removed. +# Directories listed in this section will have their own Sanitize +# called. Directories not listed will be removed in their entirety +# with rm -rf. + +Things-to-keep: + +add.d +add.lst +add.s +bitnum.d +bitnum.lst +bitnum.s +ccode.d +ccode.lst +ccode.s +cregops.d +cregops.lst +cregops.s +endmask.d +endmask.lst +endmask.s +regops.d +regops.lst +regops.s +tic80.exp + +Things-to-lose: + +Do-last: + +# End of file. diff --git a/gas/testsuite/gas/tic80/add.d b/gas/testsuite/gas/tic80/add.d new file mode 100644 index 00000000000..184d9f9fa7a --- /dev/null +++ b/gas/testsuite/gas/tic80/add.d @@ -0,0 +1,30 @@ +#objdump: -dr +#name: TIc80 signed and unsigned add instructions + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 0a 00 fb 62 add r10,r11,r12 + 4: ff 3f ac 20 add 0x3fff,r2,r4 + 8: 00 40 2c 21 add 0xffffc000,r4,r4 + c: 00 10 7b 31 add 0x4000,r5,r6 + 10: 00 40 00 00 + 14: 00 10 fb 41 add 0xffffbfff,r7,r8 + 18: ff bf ff ff + 1c: 00 10 bb 5a add 0x7fffffff,r10,r11 + 20: ff ff ff 7f + 24: 00 10 3b 6b add 0x80000000,r12,r13 + 28: 00 00 00 80 + 2c: 0a 20 fb 62 addu r10,r11,r12 + 30: ff bf ac 20 addu 0x3fff,r2,r4 + 34: 00 c0 2c 21 addu 0xffffc000,r4,r4 + 38: 00 30 7b 31 addu 0x4000,r5,r6 + 3c: 00 40 00 00 + 40: 00 30 fb 41 addu 0xffffbfff,r7,r8 + 44: ff bf ff ff + 48: 00 30 bb 5a addu 0x7fffffff,r10,r11 + 4c: ff ff ff 7f + 50: 00 30 3b 6b addu 0x80000000,r12,r13 + 54: 00 00 00 80 diff --git a/gas/testsuite/gas/tic80/add.lst b/gas/testsuite/gas/tic80/add.lst new file mode 100644 index 00000000000..cbb6aef3ab7 --- /dev/null +++ b/gas/testsuite/gas/tic80/add.lst @@ -0,0 +1,34 @@ +MVP MP Macro Assembler Version 1.13 Mon Feb 10 20:13:33 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +add.s PAGE 1 + + 1 ; Test signed and unsigned addition instruction. + 2 ; Test boundary conditions to ensure proper handling. + 3 ; Note that unsigned addition still uses signed immediates. + 4 + 5 00000000 62FB000A add r10,r11,r12 ; Register form + 6 00000004 20AC3FFF add 16383,r2,r4 ; Maximum positive short signed immediate + 7 00000008 212C4000 add -16384,r4,r4 ; Minimum negative short signed immediate + 8 0000000C 317B1000 add 16384,r5,r6 ; Minimum positive long signed immediate + 00000010 00004000 + 9 00000014 41FB1000 add -16385,r7,r8 ; Maximum negative short signed immediate + 00000018 FFFFBFFF + 10 0000001C 5ABB1000 add 2147483647,r10,r11 ; Maximum positive long signed immediate + 00000020 7FFFFFFF + 11 00000024 6B3B1000 add -2147483648,r12,r13 ; Minimum positive long signed immediate + 00000028 80000000 + 12 + 13 0000002C 62FB200A addu r10,r11,r12 ; Register form + 14 00000030 20ACBFFF addu 16383,r2,r4 ; Maximum positive short signed immediate + 15 00000034 212CC000 addu -16384,r4,r4 ; Minimum negative short signed immediate + 16 00000038 317B3000 addu 16384,r5,r6 ; Minimum positive long signed immediate + 0000003C 00004000 + 17 00000040 41FB3000 addu -16385,r7,r8 ; Maximum negative short signed immediate + 00000044 FFFFBFFF + 18 00000048 5ABB3000 addu 2147483647,r10,r11 ; Maximum positive long signed immediate + 0000004C 7FFFFFFF + 19 00000050 6B3B3000 addu -2147483648,r12,r13 ; Minimum positive long signed immediate + 00000054 80000000 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/add.s b/gas/testsuite/gas/tic80/add.s new file mode 100644 index 00000000000..6c229ed1fe4 --- /dev/null +++ b/gas/testsuite/gas/tic80/add.s @@ -0,0 +1,19 @@ +; Test signed and unsigned addition instruction. +; Test boundary conditions to ensure proper handling. +; Note that unsigned addition still uses signed immediates. + + add r10,r11,r12 ; Register form + add 16383,r2,r4 ; Maximum positive short signed immediate + add -16384,r4,r4 ; Minimum negative short signed immediate + add 16384,r5,r6 ; Minimum positive long signed immediate + add -16385,r7,r8 ; Maximum negative long signed immediate + add 2147483647,r10,r11 ; Maximum positive long signed immediate + add -2147483648,r12,r13 ; Minimum negative long signed immediate + + addu r10,r11,r12 ; Register form + addu 16383,r2,r4 ; Maximum positive short signed immediate + addu -16384,r4,r4 ; Minimum negative short signed immediate + addu 16384,r5,r6 ; Minimum positive long signed immediate + addu -16385,r7,r8 ; Maximum negative long signed immediate + addu 2147483647,r10,r11 ; Maximum positive long signed immediate + addu -2147483648,r12,r13 ; Minimum negative long signed immediate diff --git a/gas/testsuite/gas/tic80/bitnum.d b/gas/testsuite/gas/tic80/bitnum.d new file mode 100644 index 00000000000..687b03d9b88 --- /dev/null +++ b/gas/testsuite/gas/tic80/bitnum.d @@ -0,0 +1,38 @@ +#objdump: -dr +#name: TIc80 coverage of symbolic BITNUM values + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 0a 40 39 fa bbo r10,r8,eq\.b + 4: 0a 40 39 f2 bbo r10,r8,ne\.b + 8: 0a 40 39 ea bbo r10,r8,gt\.b + c: 0a 40 39 e2 bbo r10,r8,le\.b + 10: 0a 40 39 da bbo r10,r8,lt\.b + 14: 0a 40 39 d2 bbo r10,r8,ge\.b + 18: 0a 40 39 ca bbo r10,r8,hi\.b + 1c: 0a 40 39 c2 bbo r10,r8,ls\.b + 20: 0a 40 39 ba bbo r10,r8,lo\.b + 24: 0a 40 39 b2 bbo r10,r8,hs\.b + 28: 0a 40 39 aa bbo r10,r8,eq\.h + 2c: 0a 40 39 a2 bbo r10,r8,ne\.h + 30: 0a 40 39 9a bbo r10,r8,gt\.h + 34: 0a 40 39 92 bbo r10,r8,le\.h + 38: 0a 40 39 8a bbo r10,r8,lt\.h + 3c: 0a 40 39 82 bbo r10,r8,ge\.h + 40: 0a 40 39 7a bbo r10,r8,hi\.h + 44: 0a 40 39 72 bbo r10,r8,ls\.h + 48: 0a 40 39 6a bbo r10,r8,lo\.h + 4c: 0a 40 39 62 bbo r10,r8,hs\.h + 50: 0a 40 39 5a bbo r10,r8,eq\.w + 54: 0a 40 39 52 bbo r10,r8,ne\.w + 58: 0a 40 39 4a bbo r10,r8,gt\.w + 5c: 0a 40 39 42 bbo r10,r8,le\.w + 60: 0a 40 39 3a bbo r10,r8,lt\.w + 64: 0a 40 39 32 bbo r10,r8,ge\.w + 68: 0a 40 39 2a bbo r10,r8,hi\.w + 6c: 0a 40 39 22 bbo r10,r8,ls\.w + 70: 0a 40 39 1a bbo r10,r8,lo\.w + 74: 0a 40 39 12 bbo r10,r8,hs\.w diff --git a/gas/testsuite/gas/tic80/bitnum.lst b/gas/testsuite/gas/tic80/bitnum.lst new file mode 100644 index 00000000000..9b5c54c56e4 --- /dev/null +++ b/gas/testsuite/gas/tic80/bitnum.lst @@ -0,0 +1,44 @@ +MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:33 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +bitnum.s PAGE 1 + + 1 ;; Test that all the predefined symbol names for the BITNUM field + 2 ;; are properly accepted and translated to numeric values. Also + 3 ;; verifies that they are disassembled correctly as symbolics. + 4 + 5 00000000 FA39400A bbo r10,r8,eq.b + 6 00000004 F239400A bbo r10,r8,ne.b + 7 00000008 EA39400A bbo r10,r8,gt.b + 8 0000000C E239400A bbo r10,r8,le.b + 9 00000010 DA39400A bbo r10,r8,lt.b + 10 00000014 D239400A bbo r10,r8,ge.b + 11 00000018 CA39400A bbo r10,r8,hi.b + 12 0000001C C239400A bbo r10,r8,ls.b + 13 00000020 BA39400A bbo r10,r8,lo.b + 14 00000024 B239400A bbo r10,r8,hs.b + 15 + 16 00000028 AA39400A bbo r10,r8,eq.h + 17 0000002C A239400A bbo r10,r8,ne.h + 18 00000030 9A39400A bbo r10,r8,gt.h + 19 00000034 9239400A bbo r10,r8,le.h + 20 00000038 8A39400A bbo r10,r8,lt.h + 21 0000003C 8239400A bbo r10,r8,ge.h + 22 00000040 7A39400A bbo r10,r8,hi.h + 23 00000044 7239400A bbo r10,r8,ls.h + 24 00000048 6A39400A bbo r10,r8,lo.h + 25 0000004C 6239400A bbo r10,r8,hs.h + 26 + 27 00000050 5A39400A bbo r10,r8,eq.w + 28 00000054 5239400A bbo r10,r8,ne.w + 29 00000058 4A39400A bbo r10,r8,gt.w + 30 0000005C 4239400A bbo r10,r8,le.w + 31 00000060 3A39400A bbo r10,r8,lt.w + 32 00000064 3239400A bbo r10,r8,ge.w + 33 00000068 2A39400A bbo r10,r8,hi.w + 34 0000006C 2239400A bbo r10,r8,ls.w + 35 00000070 1A39400A bbo r10,r8,lo.w + 36 00000074 1239400A bbo r10,r8,hs.w + 37 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/bitnum.s b/gas/testsuite/gas/tic80/bitnum.s new file mode 100644 index 00000000000..9689315364b --- /dev/null +++ b/gas/testsuite/gas/tic80/bitnum.s @@ -0,0 +1,37 @@ +;; Test that all the predefined symbol names for the BITNUM field +;; are properly accepted and translated to numeric values. Also +;; verifies that they are disassembled correctly as symbolics. + + bbo r10,r8,eq.b + bbo r10,r8,ne.b + bbo r10,r8,gt.b + bbo r10,r8,le.b + bbo r10,r8,lt.b + bbo r10,r8,ge.b + bbo r10,r8,hi.b + bbo r10,r8,ls.b + bbo r10,r8,lo.b + bbo r10,r8,hs.b + + bbo r10,r8,eq.h + bbo r10,r8,ne.h + bbo r10,r8,gt.h + bbo r10,r8,le.h + bbo r10,r8,lt.h + bbo r10,r8,ge.h + bbo r10,r8,hi.h + bbo r10,r8,ls.h + bbo r10,r8,lo.h + bbo r10,r8,hs.h + + bbo r10,r8,eq.w + bbo r10,r8,ne.w + bbo r10,r8,gt.w + bbo r10,r8,le.w + bbo r10,r8,lt.w + bbo r10,r8,ge.w + bbo r10,r8,hi.w + bbo r10,r8,ls.w + bbo r10,r8,lo.w + bbo r10,r8,hs.w + diff --git a/gas/testsuite/gas/tic80/ccode.d b/gas/testsuite/gas/tic80/ccode.d new file mode 100644 index 00000000000..54140da1e72 --- /dev/null +++ b/gas/testsuite/gas/tic80/ccode.d @@ -0,0 +1,32 @@ +#objdump: -dr +#name: TIc80 coverage of symbolic condition code values + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 07 a0 79 01 bcnd\.a r7,r5,nev\.b + 4: 07 a0 79 09 bcnd\.a r7,r5,gt0\.b + 8: 07 a0 79 11 bcnd\.a r7,r5,eq0\.b + c: 07 a0 79 19 bcnd\.a r7,r5,ge0\.b + 10: 07 a0 79 21 bcnd\.a r7,r5,lt0\.b + 14: 07 a0 79 29 bcnd\.a r7,r5,ne0\.b + 18: 07 a0 79 31 bcnd\.a r7,r5,le0\.b + 1c: 07 a0 79 39 bcnd\.a r7,r5,alw\.b + 20: 07 a0 79 41 bcnd\.a r7,r5,nev\.h + 24: 07 a0 79 49 bcnd\.a r7,r5,gt0\.h + 28: 07 a0 79 51 bcnd\.a r7,r5,eq0\.h + 2c: 07 a0 79 59 bcnd\.a r7,r5,ge0\.h + 30: 07 a0 79 61 bcnd\.a r7,r5,lt0\.h + 34: 07 a0 79 69 bcnd\.a r7,r5,ne0\.h + 38: 07 a0 79 71 bcnd\.a r7,r5,le0\.h + 3c: 07 a0 79 79 bcnd\.a r7,r5,alw\.h + 40: 07 a0 79 81 bcnd\.a r7,r5,nev\.w + 44: 07 a0 79 89 bcnd\.a r7,r5,gt0\.w + 48: 07 a0 79 91 bcnd\.a r7,r5,eq0\.w + 4c: 07 a0 79 99 bcnd\.a r7,r5,ge0\.w + 50: 07 a0 79 a1 bcnd\.a r7,r5,lt0\.w + 54: 07 a0 79 a9 bcnd\.a r7,r5,ne0\.w + 58: 07 a0 79 b1 bcnd\.a r7,r5,le0\.w + 5c: 07 a0 79 b9 bcnd\.a r7,r5,alw\.w diff --git a/gas/testsuite/gas/tic80/ccode.lst b/gas/testsuite/gas/tic80/ccode.lst new file mode 100644 index 00000000000..26852deedf3 --- /dev/null +++ b/gas/testsuite/gas/tic80/ccode.lst @@ -0,0 +1,37 @@ +MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:49 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +ccode.s PAGE 1 + + 1 ;; Test that all the predefined symbol names for the condition + 2 ;; codes are properly accepted and translated to numeric values. + 3 ;; Also verifies that they are disassembled correctly as symbolics. + 4 + 5 00000000 0179A007 bcnd.a r7,r5,nev.b ; 00000 + 6 00000004 0979A007 bcnd.a r7,r5,gt0.b ; 00001 + 7 00000008 1179A007 bcnd.a r7,r5,eq0.b ; 00010 + 8 0000000C 1979A007 bcnd.a r7,r5,ge0.b ; 00011 + 9 00000010 2179A007 bcnd.a r7,r5,lt0.b ; 00100 + 10 00000014 2979A007 bcnd.a r7,r5,ne0.b ; 00101 + 11 00000018 3179A007 bcnd.a r7,r5,le0.b ; 00110 + 12 0000001C 3979A007 bcnd.a r7,r5,alw.b ; 00111 + 13 + 14 00000020 4179A007 bcnd.a r7,r5,nev.h ; 01000 + 15 00000024 4979A007 bcnd.a r7,r5,gt0.h ; 01001 + 16 00000028 5179A007 bcnd.a r7,r5,eq0.h ; 01010 + 17 0000002C 5979A007 bcnd.a r7,r5,ge0.h ; 01011 + 18 00000030 6179A007 bcnd.a r7,r5,lt0.h ; 01100 + 19 00000034 6979A007 bcnd.a r7,r5,ne0.h ; 01101 + 20 00000038 7179A007 bcnd.a r7,r5,le0.h ; 01110 + 21 0000003C 7979A007 bcnd.a r7,r5,alw.h ; 01111 + 22 + 23 00000040 8179A007 bcnd.a r7,r5,nev.w ; 10000 + 24 00000044 8979A007 bcnd.a r7,r5,gt0.w ; 10001 + 25 00000048 9179A007 bcnd.a r7,r5,eq0.w ; 10010 + 26 0000004C 9979A007 bcnd.a r7,r5,ge0.w ; 10011 + 27 00000050 A179A007 bcnd.a r7,r5,lt0.w ; 10100 + 28 00000054 A979A007 bcnd.a r7,r5,ne0.w ; 10101 + 29 00000058 B179A007 bcnd.a r7,r5,le0.w ; 10110 + 30 0000005C B979A007 bcnd.a r7,r5,alw.w ; 10111 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/ccode.s b/gas/testsuite/gas/tic80/ccode.s new file mode 100644 index 00000000000..9e4aac11552 --- /dev/null +++ b/gas/testsuite/gas/tic80/ccode.s @@ -0,0 +1,30 @@ +;; Test that all the predefined symbol names for the condition +;; codes are properly accepted and translated to numeric values. +;; Also verifies that they are disassembled correctly as symbolics. + + bcnd.a r7,r5,nev.b ; 00000 + bcnd.a r7,r5,gt0.b ; 00001 + bcnd.a r7,r5,eq0.b ; 00010 + bcnd.a r7,r5,ge0.b ; 00011 + bcnd.a r7,r5,lt0.b ; 00100 + bcnd.a r7,r5,ne0.b ; 00101 + bcnd.a r7,r5,le0.b ; 00110 + bcnd.a r7,r5,alw.b ; 00111 + + bcnd.a r7,r5,nev.h ; 01000 + bcnd.a r7,r5,gt0.h ; 01001 + bcnd.a r7,r5,eq0.h ; 01010 + bcnd.a r7,r5,ge0.h ; 01011 + bcnd.a r7,r5,lt0.h ; 01100 + bcnd.a r7,r5,ne0.h ; 01101 + bcnd.a r7,r5,le0.h ; 01110 + bcnd.a r7,r5,alw.h ; 01111 + + bcnd.a r7,r5,nev.w ; 10000 + bcnd.a r7,r5,gt0.w ; 10001 + bcnd.a r7,r5,eq0.w ; 10010 + bcnd.a r7,r5,ge0.w ; 10011 + bcnd.a r7,r5,lt0.w ; 10100 + bcnd.a r7,r5,ne0.w ; 10101 + bcnd.a r7,r5,le0.w ; 10110 + bcnd.a r7,r5,alw.w ; 10111 diff --git a/gas/testsuite/gas/tic80/cregops.d b/gas/testsuite/gas/tic80/cregops.d new file mode 100644 index 00000000000..5877c0f4e92 --- /dev/null +++ b/gas/testsuite/gas/tic80/cregops.d @@ -0,0 +1,68 @@ +#objdump: -dr +#name: TIc80 control register operands + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 34 00 02 10 rdcr ANASTAT,r2 + 4: 39 00 02 10 rdcr BRK1,r2 + 8: 3a 00 02 10 rdcr BRK2,r2 + c: 02 00 02 10 rdcr CONFIG,r2 + 10: 00 05 02 10 rdcr DLRU,r2 + 14: 00 04 02 10 rdcr DTAG0,r2 + 18: 01 04 02 10 rdcr DTAG1,r2 + 1c: 0a 04 02 10 rdcr DTAG10,r2 + 20: 0b 04 02 10 rdcr DTAG11,r2 + 24: 0c 04 02 10 rdcr DTAG12,r2 + 28: 0d 04 02 10 rdcr DTAG13,r2 + 2c: 0e 04 02 10 rdcr DTAG14,r2 + 30: 0f 04 02 10 rdcr DTAG15,r2 + 34: 02 04 02 10 rdcr DTAG2,r2 + 38: 03 04 02 10 rdcr DTAG3,r2 + 3c: 04 04 02 10 rdcr DTAG4,r2 + 40: 05 04 02 10 rdcr DTAG5,r2 + 44: 06 04 02 10 rdcr DTAG6,r2 + 48: 07 04 02 10 rdcr DTAG7,r2 + 4c: 08 04 02 10 rdcr DTAG8,r2 + 50: 09 04 02 10 rdcr DTAG9,r2 + 54: 33 00 02 10 rdcr ECOMCNTL,r2 + 58: 01 00 02 10 rdcr EIP,r2 + 5c: 00 00 02 10 rdcr EPC,r2 + 60: 11 00 02 10 rdcr FLTADR,r2 + 64: 14 00 02 10 rdcr FLTDTH,r2 + 68: 13 00 02 10 rdcr FLTDTL,r2 + 6c: 10 00 02 10 rdcr FLTOP,r2 + 70: 12 00 02 10 rdcr FLTTAG,r2 + 74: 08 00 02 10 rdcr FPST,r2 + 78: 06 00 02 10 rdcr IE,r2 + 7c: 00 03 02 10 rdcr ILRU,r2 + 80: 00 40 02 10 rdcr IN0P,r2 + 84: 01 40 02 10 rdcr IN1P,r2 + 88: 04 00 02 10 rdcr INTPEN,r2 + 8c: 00 02 02 10 rdcr ITAG0,r2 + 90: 01 02 02 10 rdcr ITAG1,r2 + 94: 0a 02 02 10 rdcr ITAG10,r2 + 98: 0b 02 02 10 rdcr ITAG11,r2 + 9c: 0c 02 02 10 rdcr ITAG12,r2 + a0: 0d 02 02 10 rdcr ITAG13,r2 + a4: 0e 02 02 10 rdcr ITAG14,r2 + a8: 0f 02 02 10 rdcr ITAG15,r2 + ac: 02 02 02 10 rdcr ITAG2,r2 + b0: 03 02 02 10 rdcr ITAG3,r2 + b4: 04 02 02 10 rdcr ITAG4,r2 + b8: 05 02 02 10 rdcr ITAG5,r2 + bc: 06 02 02 10 rdcr ITAG6,r2 + c0: 07 02 02 10 rdcr ITAG7,r2 + c4: 08 02 02 10 rdcr ITAG8,r2 + c8: 09 02 02 10 rdcr ITAG9,r2 + cc: 31 00 02 10 rdcr MIP,r2 + d0: 30 00 02 10 rdcr MPC,r2 + d4: 02 40 02 10 rdcr OUTP,r2 + d8: 0d 00 02 10 rdcr PKTREQ,r2 + dc: 0a 00 02 10 rdcr PPERROR,r2 + e0: 20 00 02 10 rdcr SYSSTK,r2 + e4: 21 00 02 10 rdcr SYSTMP,r2 + e8: 0e 00 02 10 rdcr TCOUNT,r2 + ec: 0f 00 02 10 rdcr TSCALE,r2 diff --git a/gas/testsuite/gas/tic80/cregops.lst b/gas/testsuite/gas/tic80/cregops.lst new file mode 100644 index 00000000000..e2a2d500a6b --- /dev/null +++ b/gas/testsuite/gas/tic80/cregops.lst @@ -0,0 +1,76 @@ +MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:56 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +cregops.s PAGE 1 + + 1 ;; Test that all predefined symbol names for control registers + 2 ;; are properly accepted and translated to numeric values. Also + 3 ;; verifies that they are diassembled correctly as symbolics. + 4 + 5 00000000 10020034 rdcr ANASTAT,r2 + 6 00000004 10020039 rdcr BRK1,r2 + 7 00000008 1002003A rdcr BRK2,r2 + 8 0000000C 10020002 rdcr CONFIG,r2 + 9 00000010 10020500 rdcr DLRU,r2 + 10 00000014 10020400 rdcr DTAG0,r2 + 11 00000018 10020401 rdcr DTAG1,r2 + 12 0000001C 1002040A rdcr DTAG10,r2 + 13 00000020 1002040B rdcr DTAG11,r2 + 14 00000024 1002040C rdcr DTAG12,r2 + 15 00000028 1002040D rdcr DTAG13,r2 + 16 0000002C 1002040E rdcr DTAG14,r2 + 17 00000030 1002040F rdcr DTAG15,r2 + 18 00000034 10020402 rdcr DTAG2,r2 + 19 00000038 10020403 rdcr DTAG3,r2 + 20 0000003C 10020404 rdcr DTAG4,r2 + 21 00000040 10020405 rdcr DTAG5,r2 + 22 00000044 10020406 rdcr DTAG6,r2 + 23 00000048 10020407 rdcr DTAG7,r2 + 24 0000004C 10020408 rdcr DTAG8,r2 + 25 00000050 10020409 rdcr DTAG9,r2 + 26 00000054 10020033 rdcr ECOMCNTL,r2 + 27 00000058 10020001 rdcr EIP,r2 + 28 0000005C 10020000 rdcr EPC,r2 + 29 00000060 10020011 rdcr FLTADR,r2 + 30 00000064 10020014 rdcr FLTDTH,r2 + 31 00000068 10020013 rdcr FLTDTL,r2 + 32 0000006C 10020010 rdcr FLTOP,r2 + 33 00000070 10020012 rdcr FLTTAG,r2 + 34 00000074 10020008 rdcr FPST,r2 + 35 00000078 10020006 rdcr IE,r2 + 36 0000007C 10020300 rdcr ILRU,r2 + 37 00000080 10024000 rdcr IN0P,r2 + 38 00000084 10024001 rdcr IN1P,r2 + 39 00000088 10020004 rdcr INTPEN,r2 + 40 0000008C 10020200 rdcr ITAG0,r2 + 41 00000090 10020201 rdcr ITAG1,r2 + 42 00000094 1002020A rdcr ITAG10,r2 + 43 00000098 1002020B rdcr ITAG11,r2 + 44 0000009C 1002020C rdcr ITAG12,r2 + 45 000000A0 1002020D rdcr ITAG13,r2 + 46 000000A4 1002020E rdcr ITAG14,r2 + 47 000000A8 1002020F rdcr ITAG15,r2 + 48 000000AC 10020202 rdcr ITAG2,r2 + 49 000000B0 10020203 rdcr ITAG3,r2 + 50 000000B4 10020204 rdcr ITAG4,r2 + 51 000000B8 10020205 rdcr ITAG5,r2 + 52 000000BC 10020206 rdcr ITAG6,r2 + 53 000000C0 10020207 rdcr ITAG7,r2 + 54 000000C4 10020208 rdcr ITAG8,r2 + 55 000000C8 10020209 rdcr ITAG9,r2 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:56 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +cregops.s PAGE 2 + + 56 000000CC 10020031 rdcr MIP,r2 + 57 000000D0 10020030 rdcr MPC,r2 + 58 000000D4 10024002 rdcr OUTP,r2 + 59 000000D8 1002000D rdcr PKTREQ,r2 + 60 000000DC 1002000A rdcr PPERROR,r2 + 61 000000E0 10020020 rdcr SYSSTK,r2 + 62 000000E4 10020021 rdcr SYSTMP,r2 + 63 000000E8 1002000E rdcr TCOUNT,r2 + 64 000000EC 1002000F rdcr TSCALE,r2 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/cregops.s b/gas/testsuite/gas/tic80/cregops.s new file mode 100644 index 00000000000..8a0adcf5652 --- /dev/null +++ b/gas/testsuite/gas/tic80/cregops.s @@ -0,0 +1,64 @@ +;; Test that all predefined symbol names for control registers +;; are properly accepted and translated to numeric values. Also +;; verifies that they are diassembled correctly as symbolics. + + rdcr ANASTAT,r2 + rdcr BRK1,r2 + rdcr BRK2,r2 + rdcr CONFIG,r2 + rdcr DLRU,r2 + rdcr DTAG0,r2 + rdcr DTAG1,r2 + rdcr DTAG10,r2 + rdcr DTAG11,r2 + rdcr DTAG12,r2 + rdcr DTAG13,r2 + rdcr DTAG14,r2 + rdcr DTAG15,r2 + rdcr DTAG2,r2 + rdcr DTAG3,r2 + rdcr DTAG4,r2 + rdcr DTAG5,r2 + rdcr DTAG6,r2 + rdcr DTAG7,r2 + rdcr DTAG8,r2 + rdcr DTAG9,r2 + rdcr ECOMCNTL,r2 + rdcr EIP,r2 + rdcr EPC,r2 + rdcr FLTADR,r2 + rdcr FLTDTH,r2 + rdcr FLTDTL,r2 + rdcr FLTOP,r2 + rdcr FLTTAG,r2 + rdcr FPST,r2 + rdcr IE,r2 + rdcr ILRU,r2 + rdcr IN0P,r2 + rdcr IN1P,r2 + rdcr INTPEN,r2 + rdcr ITAG0,r2 + rdcr ITAG1,r2 + rdcr ITAG10,r2 + rdcr ITAG11,r2 + rdcr ITAG12,r2 + rdcr ITAG13,r2 + rdcr ITAG14,r2 + rdcr ITAG15,r2 + rdcr ITAG2,r2 + rdcr ITAG3,r2 + rdcr ITAG4,r2 + rdcr ITAG5,r2 + rdcr ITAG6,r2 + rdcr ITAG7,r2 + rdcr ITAG8,r2 + rdcr ITAG9,r2 + rdcr MIP,r2 + rdcr MPC,r2 + rdcr OUTP,r2 + rdcr PKTREQ,r2 + rdcr PPERROR,r2 + rdcr SYSSTK,r2 + rdcr SYSTMP,r2 + rdcr TCOUNT,r2 + rdcr TSCALE,r2 diff --git a/gas/testsuite/gas/tic80/endmask.d b/gas/testsuite/gas/tic80/endmask.d new file mode 100644 index 00000000000..2d79c137f02 --- /dev/null +++ b/gas/testsuite/gas/tic80/endmask.d @@ -0,0 +1,41 @@ +#objdump: -dr +#name: TIc80 coverage of shift instruction ENDMASK field + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 05 00 c7 49 shl 5,0,r7,r9 + 4: 25 00 c7 49 shl 5,1,r7,r9 + 8: 45 00 c7 49 shl 5,2,r7,r9 + c: 65 00 c7 49 shl 5,3,r7,r9 + 10: 85 00 c7 49 shl 5,4,r7,r9 + 14: a5 00 c7 49 shl 5,5,r7,r9 + 18: c5 00 c7 49 shl 5,6,r7,r9 + 1c: e5 00 c7 49 shl 5,7,r7,r9 + 20: 05 01 c7 49 shl 5,8,r7,r9 + 24: 25 01 c7 49 shl 5,9,r7,r9 + 28: 45 01 c7 49 shl 5,10,r7,r9 + 2c: 65 01 c7 49 shl 5,11,r7,r9 + 30: 85 01 c7 49 shl 5,12,r7,r9 + 34: a5 01 c7 49 shl 5,13,r7,r9 + 38: c5 01 c7 49 shl 5,14,r7,r9 + 3c: e5 01 c7 49 shl 5,15,r7,r9 + 40: 05 02 c7 49 shl 5,16,r7,r9 + 44: 25 02 c7 49 shl 5,17,r7,r9 + 48: 45 02 c7 49 shl 5,18,r7,r9 + 4c: 65 02 c7 49 shl 5,19,r7,r9 + 50: 85 02 c7 49 shl 5,20,r7,r9 + 54: a5 02 c7 49 shl 5,21,r7,r9 + 58: c5 02 c7 49 shl 5,22,r7,r9 + 5c: e5 02 c7 49 shl 5,23,r7,r9 + 60: 05 03 c7 49 shl 5,24,r7,r9 + 64: 25 03 c7 49 shl 5,25,r7,r9 + 68: 45 03 c7 49 shl 5,26,r7,r9 + 6c: 65 03 c7 49 shl 5,27,r7,r9 + 70: 85 03 c7 49 shl 5,28,r7,r9 + 74: a5 03 c7 49 shl 5,29,r7,r9 + 78: c5 03 c7 49 shl 5,30,r7,r9 + 7c: e5 03 c7 49 shl 5,31,r7,r9 + 80: 05 00 c7 49 shl 5,0,r7,r9 diff --git a/gas/testsuite/gas/tic80/endmask.lst b/gas/testsuite/gas/tic80/endmask.lst new file mode 100644 index 00000000000..e41f78652ce --- /dev/null +++ b/gas/testsuite/gas/tic80/endmask.lst @@ -0,0 +1,45 @@ +MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:29 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +endmask.s PAGE 1 + + 1 ;; Test all possible combinations of the endmask in bits 5-9. + 2 ;; The mask that is used is computed as 2**bits-1 where bits + 3 ;; are the bits 5-9 from the instruction. Note that 0 and 32 + 4 ;; are treated identically, and disassembled as 0. + 5 + 6 00000000 49C70005 sl.iz 5,0,r7,r9 + 7 00000004 49C70025 sl.iz 5,1,r7,r9 + 8 00000008 49C70045 sl.iz 5,2,r7,r9 + 9 0000000C 49C70065 sl.iz 5,3,r7,r9 + 10 00000010 49C70085 sl.iz 5,4,r7,r9 + 11 00000014 49C700A5 sl.iz 5,5,r7,r9 + 12 00000018 49C700C5 sl.iz 5,6,r7,r9 + 13 0000001C 49C700E5 sl.iz 5,7,r7,r9 + 14 00000020 49C70105 sl.iz 5,8,r7,r9 + 15 00000024 49C70125 sl.iz 5,9,r7,r9 + 16 00000028 49C70145 sl.iz 5,10,r7,r9 + 17 0000002C 49C70165 sl.iz 5,11,r7,r9 + 18 00000030 49C70185 sl.iz 5,12,r7,r9 + 19 00000034 49C701A5 sl.iz 5,13,r7,r9 + 20 00000038 49C701C5 sl.iz 5,14,r7,r9 + 21 0000003C 49C701E5 sl.iz 5,15,r7,r9 + 22 00000040 49C70205 sl.iz 5,16,r7,r9 + 23 00000044 49C70225 sl.iz 5,17,r7,r9 + 24 00000048 49C70245 sl.iz 5,18,r7,r9 + 25 0000004C 49C70265 sl.iz 5,19,r7,r9 + 26 00000050 49C70285 sl.iz 5,20,r7,r9 + 27 00000054 49C702A5 sl.iz 5,21,r7,r9 + 28 00000058 49C702C5 sl.iz 5,22,r7,r9 + 29 0000005C 49C702E5 sl.iz 5,23,r7,r9 + 30 00000060 49C70305 sl.iz 5,24,r7,r9 + 31 00000064 49C70325 sl.iz 5,25,r7,r9 + 32 00000068 49C70345 sl.iz 5,26,r7,r9 + 33 0000006C 49C70365 sl.iz 5,27,r7,r9 + 34 00000070 49C70385 sl.iz 5,28,r7,r9 + 35 00000074 49C703A5 sl.iz 5,29,r7,r9 + 36 00000078 49C703C5 sl.iz 5,30,r7,r9 + 37 0000007C 49C703E5 sl.iz 5,31,r7,r9 + 38 00000080 49C70005 sl.iz 5,32,r7,r9 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/endmask.s b/gas/testsuite/gas/tic80/endmask.s new file mode 100644 index 00000000000..a36aedebafe --- /dev/null +++ b/gas/testsuite/gas/tic80/endmask.s @@ -0,0 +1,38 @@ +;; Test all possible combinations of the endmask in bits 5-9. +;; The mask that is used is computed as 2**bits-1 where bits +;; are the bits 5-9 from the instruction. Note that 0 and 32 +;; are treated identically, and disassembled as 0. + + sl.iz 5,0,r7,r9 + sl.iz 5,1,r7,r9 + sl.iz 5,2,r7,r9 + sl.iz 5,3,r7,r9 + sl.iz 5,4,r7,r9 + sl.iz 5,5,r7,r9 + sl.iz 5,6,r7,r9 + sl.iz 5,7,r7,r9 + sl.iz 5,8,r7,r9 + sl.iz 5,9,r7,r9 + sl.iz 5,10,r7,r9 + sl.iz 5,11,r7,r9 + sl.iz 5,12,r7,r9 + sl.iz 5,13,r7,r9 + sl.iz 5,14,r7,r9 + sl.iz 5,15,r7,r9 + sl.iz 5,16,r7,r9 + sl.iz 5,17,r7,r9 + sl.iz 5,18,r7,r9 + sl.iz 5,19,r7,r9 + sl.iz 5,20,r7,r9 + sl.iz 5,21,r7,r9 + sl.iz 5,22,r7,r9 + sl.iz 5,23,r7,r9 + sl.iz 5,24,r7,r9 + sl.iz 5,25,r7,r9 + sl.iz 5,26,r7,r9 + sl.iz 5,27,r7,r9 + sl.iz 5,28,r7,r9 + sl.iz 5,29,r7,r9 + sl.iz 5,30,r7,r9 + sl.iz 5,31,r7,r9 + sl.iz 5,32,r7,r9 diff --git a/gas/testsuite/gas/tic80/regops.d b/gas/testsuite/gas/tic80/regops.d new file mode 100644 index 00000000000..96d8bdbc295 --- /dev/null +++ b/gas/testsuite/gas/tic80/regops.d @@ -0,0 +1,188 @@ +#objdump: -dr +#name: TIc80 register operands + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <.text>: + 0: 03 00 3b 29 add r3,r4,r5 + 4: 03 20 3b 29 addu r3,r4,r5 + 8: 05 20 32 11 and r5,r4,r2 + c: 05 20 32 11 and r5,r4,r2 + 10: 0a 00 33 73 and\.ff r10,r12,r14 + 14: 0a 80 32 73 and\.ft r10,r12,r14 + 18: 0a 40 32 73 and\.tf r10,r12,r14 + 1c: 0a 40 39 1a bbo r10,r8,lo\.w + 20: 0a 60 39 fa bbo\.a r10,r8,eq\.b + 24: 0a 00 39 22 bbz r10,r8,ls\.w + 28: 0a 20 39 2a bbz\.a r10,r8,hi\.w + 2c: 04 80 b9 21 bcnd r4,r6,lt0\.b + 30: 04 a0 b9 21 bcnd\.a r4,r6,lt0\.b + 34: 06 00 39 00 br r6 + 38: 06 20 39 00 br\.a r6 + 3c: 0a 00 03 00 brcr PPERROR + 40: 06 00 38 f8 bsr r6,r31 + 44: 06 20 38 f8 bsr\.a r6,r31 + 48: 07 40 30 00 cmnd r7 + 4c: 03 00 3a 29 cmp r3,r4,r5 + 50: 08 00 b7 02 dcachec r8\(r10\) + 54: 08 00 b7 0a dcachef r8\(r10\) + 58: 04 04 b4 41 dld\.b r4\(r6\),r8 + 5c: 04 24 b4 41 dld\.h r4\(r6\),r8 + 60: 04 44 b4 41 dld r4\(r6\),r8 + 64: 04 64 b4 41 dld\.d r4\(r6\),r8 + 68: 04 04 b5 41 dld\.ub r4\(r6\),r8 + 6c: 04 24 b5 41 dld\.uh r4\(r6\),r8 + 70: 04 04 b6 41 dst\.b r4\(r6\),r8 + 74: 04 24 b6 41 dst\.h r4\(r6\),r8 + 78: 04 44 b6 41 dst r4\(r6\),r8 + 7c: 04 64 b6 41 dst\.d r4\(r6\),r8 + 80: 05 20 30 08 etrap r5 + 84: e3 47 71 31 exts r3,31,r5,r6 + 88: c2 07 71 49 extu r2,30,r5,r9 + 8c: 02 00 3e 31 fadd\.sss r2,r4,r6 + 90: 02 02 3e 31 fadd\.ssd r2,r4,r6 + 94: 82 02 3e 31 fadd\.sdd r2,r4,r6 + 98: 22 02 3e 31 fadd\.dsd r2,r4,r6 + 9c: a2 02 3e 31 fadd\.ddd r2,r4,r6 + a0: 04 a0 be 41 fcmp\.ss r4,r6,r8 + a4: 84 a0 be 41 fcmp\.sd r4,r6,r8 + a8: 24 a0 be 41 fcmp\.ds r4,r6,r8 + ac: a4 a0 be 41 fcmp\.dd r4,r6,r8 + b0: 02 60 3e 31 fdiv\.sss r2,r4,r6 + b4: 02 62 3e 31 fdiv\.ssd r2,r4,r6 + b8: 82 62 3e 31 fdiv\.sdd r2,r4,r6 + bc: 22 62 3e 31 fdiv\.dsd r2,r4,r6 + c0: a2 62 3e 31 fdiv\.ddd r2,r4,r6 + c4: 02 40 3e 31 fmpy\.sss r2,r4,r6 + c8: 02 42 3e 31 fmpy\.ssd r2,r4,r6 + cc: 82 42 3e 31 fmpy\.sdd r2,r4,r6 + d0: 22 42 3e 31 fmpy\.dsd r2,r4,r6 + d4: a2 42 3e 31 fmpy\.ddd r2,r4,r6 + d8: 42 45 3e 31 fmpy\.iii r2,r4,r6 + dc: e2 47 3e 31 fmpy\.uuu r2,r4,r6 + e0: 84 81 3e 30 frndm\.ss r4,r6 + e4: 84 83 3e 30 frndm\.sd r4,r6 + e8: 84 85 3e 30 frndm\.si r4,r6 + ec: 84 87 3e 30 frndm\.su r4,r6 + f0: a2 81 3e 40 frndm\.ds r2,r8 + f4: a2 83 3e 40 frndm\.dd r2,r8 + f8: a2 85 3e 40 frndm\.di r2,r8 + fc: a2 87 3e 40 frndm\.du r2,r8 + 100: c4 81 3e 30 frndm\.is r4,r6 + 104: c4 83 3e 30 frndm\.id r4,r6 + 108: e2 81 3e 40 frndm\.us r2,r8 + 10c: e2 83 3e 40 frndm\.ud r2,r8 + 110: 04 80 3e 30 frndn\.ss r4,r6 + 114: 04 82 3e 30 frndn\.sd r4,r6 + 118: 04 84 3e 30 frndn\.si r4,r6 + 11c: 04 86 3e 30 frndn\.su r4,r6 + 120: 22 80 3e 40 frndn\.ds r2,r8 + 124: 22 82 3e 40 frndn\.dd r2,r8 + 128: 22 84 3e 40 frndn\.di r2,r8 + 12c: 22 86 3e 40 frndn\.du r2,r8 + 130: 44 80 3e 30 frndn\.is r4,r6 + 134: 44 82 3e 30 frndn\.id r4,r6 + 138: 62 80 3e 40 frndn\.us r2,r8 + 13c: 62 82 3e 40 frndn\.ud r2,r8 + 140: 04 81 3e 30 frndp\.ss r4,r6 + 144: 04 83 3e 30 frndp\.sd r4,r6 + 148: 04 85 3e 30 frndp\.si r4,r6 + 14c: 04 87 3e 30 frndp\.su r4,r6 + 150: 22 81 3e 40 frndp\.ds r2,r8 + 154: 22 83 3e 40 frndp\.dd r2,r8 + 158: 22 85 3e 40 frndp\.di r2,r8 + 15c: 22 87 3e 40 frndp\.du r2,r8 + 160: 44 81 3e 30 frndp\.is r4,r6 + 164: 44 83 3e 30 frndp\.id r4,r6 + 168: 62 81 3e 40 frndp\.us r2,r8 + 16c: 62 83 3e 40 frndp\.ud r2,r8 + 170: 84 80 3e 30 frndz\.ss r4,r6 + 174: 84 82 3e 30 frndz\.sd r4,r6 + 178: 84 84 3e 30 frndz\.si r4,r6 + 17c: 84 86 3e 30 frndz\.su r4,r6 + 180: a2 80 3e 40 frndz\.ds r2,r8 + 184: a2 82 3e 40 frndz\.dd r2,r8 + 188: a2 84 3e 40 frndz\.di r2,r8 + 18c: a2 86 3e 40 frndz\.du r2,r8 + 190: c4 80 3e 30 frndz\.is r4,r6 + 194: c4 82 3e 30 frndz\.id r4,r6 + 198: e2 80 3e 40 frndz\.us r2,r8 + 19c: e2 82 3e 40 frndz\.ud r2,r8 + 1a0: 06 e0 3e 40 fsqrt\.ss r6,r8 + 1a4: 06 e2 3e 40 fsqrt\.sd r6,r8 + 1a8: 26 e2 3e 40 fsqrt\.dd r6,r8 + 1ac: 02 20 3e 31 fsub\.sss r2,r4,r6 + 1b0: 02 22 3e 31 fsub\.ssd r2,r4,r6 + 1b4: 82 22 3e 31 fsub\.sdd r2,r4,r6 + 1b8: 22 22 3e 31 fsub\.dsd r2,r4,r6 + 1bc: a2 22 3e 31 fsub\.ddd r2,r4,r6 + 1c0: e4 e3 31 52 ins r4,31,r8,r10 + 1c4: 04 80 b8 41 jsr r4\(r6\),r8 + 1c8: 04 a0 b8 41 jsr\.a r4\(r6\),r8 + 1cc: 04 00 b4 41 ld\.b r4\(r6\),r8 + 1d0: 04 20 b4 41 ld\.h r4\(r6\),r8 + 1d4: 04 40 b4 41 ld r4\(r6\),r8 + 1d8: 04 60 b4 41 ld\.d r4\(r6\),r8 + 1dc: 04 00 b5 41 ld\.ub r4\(r6\),r8 + 1e0: 04 20 b5 41 ld\.uh r4\(r6\),r8 + 1e4: 00 00 ff 41 lmo r7,r8 + 1e8: 01 e0 b2 18 or\.tt r1,r2,r3 + 1ec: 01 e0 b2 18 or\.tt r1,r2,r3 + 1f0: 01 c0 b3 18 or\.ff r1,r2,r3 + 1f4: 01 a0 b3 18 or\.ft r1,r2,r3 + 1f8: 01 60 b3 18 or\.tf r1,r2,r3 + 1fc: 06 80 30 20 rdcr r6,r4 + 200: 00 20 3f 29 rmo r4,r5 + 204: e2 03 31 52 rotl r2,31,r8,r10 + 208: e8 07 b1 30 extu r8,31,r2,r6 + 20c: e4 c3 b1 30 shl r4,31,r2,r6 + 210: 84 01 71 31 rotl r4,12,r5,r6 + 214: 84 21 71 31 sl\.dm r4,12,r5,r6 + 218: 84 41 71 31 sl\.ds r4,12,r5,r6 + 21c: 84 61 71 31 sl\.ez r4,12,r5,r6 + 220: 84 81 71 31 sl\.em r4,12,r5,r6 + 224: 84 a1 71 31 sl\.es r4,12,r5,r6 + 228: 84 c1 71 31 shl r4,12,r5,r6 + 22c: 84 e1 71 31 ins r4,12,r5,r6 + 230: 84 09 71 31 sli\.dz r4,12,r5,r6 + 234: 84 29 71 31 sli\.dm r4,12,r5,r6 + 238: 84 49 71 31 sli\.ds r4,12,r5,r6 + 23c: 84 69 71 31 sli\.ez r4,12,r5,r6 + 240: 84 89 71 31 sli\.em r4,12,r5,r6 + 244: 84 a9 71 31 sli\.es r4,12,r5,r6 + 248: 84 c9 71 31 sli\.iz r4,12,r5,r6 + 24c: 84 e9 71 31 sli\.im r4,12,r5,r6 + 250: 84 05 71 31 extu r4,12,r5,r6 + 254: 84 25 71 31 sr\.dm r4,12,r5,r6 + 258: 84 45 71 31 exts r4,12,r5,r6 + 25c: 84 65 71 31 srl r4,12,r5,r6 + 260: 84 85 71 31 sr\.em r4,12,r5,r6 + 264: 84 a5 71 31 sra r4,12,r5,r6 + 268: 84 c5 71 31 sr\.iz r4,12,r5,r6 + 26c: 84 e5 71 31 sr\.im r4,12,r5,r6 + 270: 04 a4 b1 41 sra r4,0,r6,r8 + 274: 84 0d 71 31 sri\.dz r4,12,r5,r6 + 278: 84 2d 71 31 sri\.dm r4,12,r5,r6 + 27c: 84 4d 71 31 sri\.ds r4,12,r5,r6 + 280: 84 6d 71 31 sri\.ez r4,12,r5,r6 + 284: 84 8d 71 31 sri\.em r4,12,r5,r6 + 288: 84 ad 71 31 sri\.es r4,12,r5,r6 + 28c: 84 cd 71 31 sri\.iz r4,12,r5,r6 + 290: 84 ed 71 31 sri\.im r4,12,r5,r6 + 294: 04 64 b1 41 srl r4,0,r6,r8 + 298: 04 00 b6 41 st\.b r4\(r6\),r8 + 29c: 04 20 b6 41 st\.h r4\(r6\),r8 + 2a0: 04 40 b6 41 st r4\(r6\),r8 + 2a4: 04 60 b6 41 st\.d r4\(r6\),r8 + 2a8: 07 40 3b 4a sub r7,r8,r9 + 2ac: 07 60 3b 4a subu r7,r8,r9 + 2b0: 08 a0 b0 21 swcr r8,r6,r4 + 2b4: 0a 20 30 00 trap r10 + 2b8: 02 00 3c 01 vadd\.ss r2,r4,r4 + 2bc: 82 00 bc 01 vadd\.sd r2,r6,r6 + 2c0: a2 00 bc 02 vadd\.dd r2,r10,r10 + 2c4: 06 a0 70 01 wrcr r6,r5 + 2c8: 05 20 b3 39 xnor r5,r6,r7 + 2cc: 07 c0 32 4a xor r7,r8,r9 diff --git a/gas/testsuite/gas/tic80/regops.lst b/gas/testsuite/gas/tic80/regops.lst new file mode 100644 index 00000000000..4c78adc1dc9 --- /dev/null +++ b/gas/testsuite/gas/tic80/regops.lst @@ -0,0 +1,264 @@ +MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 1 + + 1 ;; Simple register forms + 2 ;; Those instructions which also use an immediate just use a constant. + 3 + 4 00000000 .text + 5 + 6 00000000 293B0003 add r3,r4,r5 + 7 00000004 293B2003 addu r3,r4,r5 + 8 00000008 11322005 and r5,r4,r2 + 9 0000000C 11322005 and.tt r5,r4,r2 + 10 00000010 7333000A and.ff r10,r12,r14 + 11 00000014 7332800A and.ft r10,r12,r14 + 12 00000018 7332400A and.tf r10,r12,r14 + 13 0000001C 1A39400A bbo r10,r8,lo.w + 14 00000020 FA39600A bbo.a r10,r8,eq.b + 15 00000024 2239000A bbz r10,r8,ls.w + 16 00000028 2A39200A bbz.a r10,r8,hi.w + 17 0000002C 21B98004 bcnd r4,r6,lt0.b + 18 00000030 21B9A004 bcnd.a r4,r6,lt0.b + 19 00000034 00390006 br r6 + 20 00000038 00392006 br.a r6 + 21 0000003C 0003000A brcr 10 + 22 00000040 F8380006 bsr r6,r31 + 23 00000044 F8382006 bsr.a r6,r31 + 24 00000048 00304007 cmnd r7 + 25 0000004C 293A0003 cmp r3,r4,r5 + 26 00000050 02B70008 dcachec r8(r10) + 27 00000054 0AB70008 dcachef r8(r10) + 28 00000058 41B40404 dld.b r4(r6),r8 + 29 0000005C 41B42404 dld.h r4(r6),r8 + 30 00000060 41B44404 dld r4(r6),r8 + 31 00000064 41B46404 dld.d r4(r6),r8 + 32 00000068 41B50404 dld.ub r4(r6),r8 + 33 0000006C 41B52404 dld.uh r4(r6),r8 + 34 00000070 41B60404 dst.b r4(r6),r8 + 35 00000074 41B62404 dst.h r4(r6),r8 + 36 00000078 41B64404 dst r4(r6),r8 + 37 0000007C 41B66404 dst.d r4(r6),r8 + 38 00000080 08302005 etrap r5 + 39 00000084 317147E3 exts r3,31,r5,r6 + 40 00000088 497107C2 extu r2,30,r5,r9 + 41 0000008C 313E0002 fadd.sss r2,r4,r6 + 42 00000090 313E0202 fadd.ssd r2,r4,r6 + 43 00000094 313E0282 fadd.sdd r2,r4,r6 + 44 00000098 313E0222 fadd.dsd r2,r4,r6 + 45 0000009C 313E02A2 fadd.ddd r2,r4,r6 + 46 000000A0 41BEA004 fcmp.ss r4,r6,r8 + 47 000000A4 41BEA084 fcmp.sd r4,r6,r8 + 48 000000A8 41BEA024 fcmp.ds r4,r6,r8 + 49 000000AC 41BEA0A4 fcmp.dd r4,r6,r8 + 50 000000B0 313E6002 fdiv.sss r2,r4,r6 + 51 000000B4 313E6202 fdiv.ssd r2,r4,r6 + 52 000000B8 313E6282 fdiv.sdd r2,r4,r6 + 53 000000BC 313E6222 fdiv.dsd r2,r4,r6 + 54 000000C0 313E62A2 fdiv.ddd r2,r4,r6 + 55 000000C4 313E4002 fmpy.sss r2,r4,r6 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 2 + + 56 000000C8 313E4202 fmpy.ssd r2,r4,r6 + 57 000000CC 313E4282 fmpy.sdd r2,r4,r6 + 58 000000D0 313E4222 fmpy.dsd r2,r4,r6 + 59 000000D4 313E42A2 fmpy.ddd r2,r4,r6 + 60 000000D8 313E4542 fmpy.iii r2,r4,r6 + 61 000000DC 313E47E2 fmpy.uuu r2,r4,r6 + 62 000000E0 303E8184 frndm.ss r4,r6 + 63 000000E4 303E8384 frndm.sd r4,r6 + 64 000000E8 303E8584 frndm.si r4,r6 + 65 000000EC 303E8784 frndm.su r4,r6 + 66 000000F0 403E81A2 frndm.ds r2,r8 + 67 000000F4 403E83A2 frndm.dd r2,r8 + 68 000000F8 403E85A2 frndm.di r2,r8 + 69 000000FC 403E87A2 frndm.du r2,r8 + 70 00000100 303E81C4 frndm.is r4,r6 + 71 00000104 303E83C4 frndm.id r4,r6 + 72 00000108 403E81E2 frndm.us r2,r8 + 73 0000010C 403E83E2 frndm.ud r2,r8 + 74 00000110 303E8004 frndn.ss r4,r6 + 75 00000114 303E8204 frndn.sd r4,r6 + 76 00000118 303E8404 frndn.si r4,r6 + 77 0000011C 303E8604 frndn.su r4,r6 + 78 00000120 403E8022 frndn.ds r2,r8 + 79 00000124 403E8222 frndn.dd r2,r8 + 80 00000128 403E8422 frndn.di r2,r8 + 81 0000012C 403E8622 frndn.du r2,r8 + 82 00000130 303E8044 frndn.is r4,r6 + 83 00000134 303E8244 frndn.id r4,r6 + 84 00000138 403E8062 frndn.us r2,r8 + 85 0000013C 403E8262 frndn.ud r2,r8 + 86 00000140 303E8104 frndp.ss r4,r6 + 87 00000144 303E8304 frndp.sd r4,r6 + 88 00000148 303E8504 frndp.si r4,r6 + 89 0000014C 303E8704 frndp.su r4,r6 + 90 00000150 403E8122 frndp.ds r2,r8 + 91 00000154 403E8322 frndp.dd r2,r8 + 92 00000158 403E8522 frndp.di r2,r8 + 93 0000015C 403E8722 frndp.du r2,r8 + 94 00000160 303E8144 frndp.is r4,r6 + 95 00000164 303E8344 frndp.id r4,r6 + 96 00000168 403E8162 frndp.us r2,r8 + 97 0000016C 403E8362 frndp.ud r2,r8 + 98 00000170 303E8084 frndz.ss r4,r6 + 99 00000174 303E8284 frndz.sd r4,r6 + 100 00000178 303E8484 frndz.si r4,r6 + 101 0000017C 303E8684 frndz.su r4,r6 + 102 00000180 403E80A2 frndz.ds r2,r8 + 103 00000184 403E82A2 frndz.dd r2,r8 + 104 00000188 403E84A2 frndz.di r2,r8 + 105 0000018C 403E86A2 frndz.du r2,r8 + 106 00000190 303E80C4 frndz.is r4,r6 + 107 00000194 303E82C4 frndz.id r4,r6 + 108 00000198 403E80E2 frndz.us r2,r8 + 109 0000019C 403E82E2 frndz.ud r2,r8 + 110 000001A0 403EE006 fsqrt.ss r6,r8 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 3 + + 111 000001A4 403EE206 fsqrt.sd r6,r8 + 112 000001A8 403EE226 fsqrt.dd r6,r8 + 113 000001AC 313E2002 fsub.sss r2,r4,r6 + 114 000001B0 313E2202 fsub.ssd r2,r4,r6 + 115 000001B4 313E2282 fsub.sdd r2,r4,r6 + 116 000001B8 313E2222 fsub.dsd r2,r4,r6 + 117 000001BC 313E22A2 fsub.ddd r2,r4,r6 + 118 000001C0 5231E3E4 ins r4,31,r8,r10 + 119 000001C4 41B88004 jsr r4(r6),r8 + 120 000001C8 41B8A004 jsr.a r4(r6),r8 + 121 000001CC 41B40004 ld.b r4(r6),r8 + 122 000001D0 41B42004 ld.h r4(r6),r8 + 123 000001D4 41B44004 ld r4(r6),r8 + 124 000001D8 41B46004 ld.d r4(r6),r8 + 125 000001DC 41B50004 ld.ub r4(r6),r8 + 126 000001E0 41B52004 ld.uh r4(r6),r8 + 127 000001E4 41FF0007 lmo r7,r8 + 128 000001E8 18B2E001 or r1,r2,r3 + 129 000001EC 18B2E001 or.tt r1,r2,r3 + 130 000001F0 18B3C001 or.ff r1,r2,r3 + 131 000001F4 18B3A001 or.ft r1,r2,r3 + 132 000001F8 18B36001 or.tf r1,r2,r3 + 133 000001FC 20308006 rdcr r6,r4 + 134 00000200 293F2004 rmo r4,r5 + 135 00000204 523103E2 rotl r2,31,r8,r10 + 136 00000208 30B107E8 rotr r8,31,r2,r6 + 137 0000020C 30B1C3E4 shl r4,31,r2,r6 + 138 00000210 31710184 sl.dz r4,12,r5,r6 + 139 00000214 31712184 sl.dm r4,12,r5,r6 + 140 00000218 31714184 sl.ds r4,12,r5,r6 + 141 0000021C 31716184 sl.ez r4,12,r5,r6 + 142 00000220 31718184 sl.em r4,12,r5,r6 + 143 00000224 3171A184 sl.es r4,12,r5,r6 + 144 00000228 3171C184 sl.iz r4,12,r5,r6 + 145 0000022C 3171E184 sl.im r4,12,r5,r6 + 146 00000230 31710984 sli.dz r4,12,r5,r6 + 147 00000234 31712984 sli.dm r4,12,r5,r6 + 148 00000238 31714984 sli.ds r4,12,r5,r6 + 149 0000023C 31716984 sli.ez r4,12,r5,r6 + 150 00000240 31718984 sli.em r4,12,r5,r6 + 151 00000244 3171A984 sli.es r4,12,r5,r6 + 152 00000248 3171C984 sli.iz r4,12,r5,r6 + 153 0000024C 3171E984 sli.im r4,12,r5,r6 + 154 00000250 31710584 sr.dz r4,12,r5,r6 + 155 00000254 31712584 sr.dm r4,12,r5,r6 + 156 00000258 31714584 sr.ds r4,12,r5,r6 + 157 0000025C 31716584 sr.ez r4,12,r5,r6 + 158 00000260 31718584 sr.em r4,12,r5,r6 + 159 00000264 3171A584 sr.es r4,12,r5,r6 + 160 00000268 3171C584 sr.iz r4,12,r5,r6 + 161 0000026C 3171E584 sr.im r4,12,r5,r6 + 162 00000270 41B1A404 sra r4,32,r6,r8 + 163 00000274 31710D84 sri.dz r4,12,r5,r6 + 164 00000278 31712D84 sri.dm r4,12,r5,r6 + 165 0000027C 31714D84 sri.ds r4,12,r5,r6 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 4 + + 166 00000280 31716D84 sri.ez r4,12,r5,r6 + 167 00000284 31718D84 sri.em r4,12,r5,r6 + 168 00000288 3171AD84 sri.es r4,12,r5,r6 + 169 0000028C 3171CD84 sri.iz r4,12,r5,r6 + 170 00000290 3171ED84 sri.im r4,12,r5,r6 + 171 00000294 41B16404 srl r4,32,r6,r8 + 172 00000298 41B60004 st.b r4(r6),r8 + 173 0000029C 41B62004 st.h r4(r6),r8 + 174 000002A0 41B64004 st r4(r6),r8 + 175 000002A4 41B66004 st.d r4(r6),r8 + 176 000002A8 4A3B4007 sub r7,r8,r9 + 177 000002AC 4A3B6007 subu r7,r8,r9 + 178 000002B0 21B0A008 swcr r8,r6,r4 + 179 000002B4 0030200A trap r10 + 180 000002B8 013C0002 vadd.ss r2,r4,r4 + 181 000002BC 01BC0082 vadd.sd r2,r6,r6 + 182 000002C0 02BC00A2 vadd.dd r2,r10,r10 + 183 ; vld0.s r6 + 184 ; vld1.s r7 + 185 ; vld0.d r6 + 186 ; vld1.d r8 + 187 ; vmac.sss r7,r9,0,a3 + 188 ; vmac.sss r7,r9,0,r10 + 189 ; vmac.sss r7,r9,a1,a3 + 190 ; vmac.sss r7,r9,a3,r10 + 191 ; vmac.ssd r7,r9,0,a0 + 192 ; vmac.ssd r7,r9,0,r10 + 193 ; vmac.ssd r7,r9,a1,a2 + 194 ; vmac.ssd r7,r9,a3,r10 + 195 ; vmpy.ss r1,r3,r3 + 196 ; vmpy.sd r5,r6,r6 + 197 ; vmpy.dd r2,r4,r4 + 198 ; vmsc.sss r7,r9,0,a0 + 199 ; vmsc.sss r7,r9,0,r10 + 200 ; vmsc.sss r7,r9,a0,a1 + 201 ; vmsc.sss r7,r9,a3,r10 + 202 ; vmsc.ssd r7,r9,0,a0 + 203 ; vmsc.ssd r7,r9,0,r10 + 204 ; vmsc.ssd r7,r9,a0,a1 + 205 ; vmsc.ssd r7,r9,a3,r10 + 206 ; vmsub.ss r6,a2,a4 + 207 ; vmsub.sd r6,a2,a4 + 208 ; vmsub.ss r4,a4,r6 + 209 ; vmsub.sd r4,a4,r6 + 210 ; vrnd.si r4,r6 + 211 ; vrnd.si r4,a0 + 212 ; vrnd.su r4,r6 + 213 ; vrnd.su r4,a0 + 214 ; vrnd.ss r4,r6 + 215 ; vrnd.ss r4,a0 + 216 ; vrnd.sd r4,r6 + 217 ; vrnd.sd r4,a0 + 218 ; vrnd.di r4,r6 + 219 ; vrnd.di r4,a0 + 220 ; vrnd.du r4,r6 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 5 + + 221 ; vrnd.du r4,a0 + 222 ; vrnd.ds r4,r6 + 223 ; vrnd.ds r4,a0 + 224 ; vrnd.dd r4,r6 + 225 ; vrnd.dd r4,a0 + 226 ; vrnd.is r4,r6 + 227 ; vrnd.id r4,r6 + 228 ; vrnd.us r4,r6 + 229 ; vrnd.ud r4,r6 + 230 ; vst.s r6 + 231 ; vst.d r6 + 232 ; vsub.ss r2,r4,r6 + 233 ; vsub.sd r2,r4,r6 + 234 ; vsub.dd r2,r4,r6 + 235 000002C4 0170A006 wrcr r6,r5 + 236 000002C8 39B32005 xnor r5,r6,r7 + 237 000002CC 4A32C007 xor r7,r8,r9 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/regops.s b/gas/testsuite/gas/tic80/regops.s new file mode 100644 index 00000000000..f4f93523c31 --- /dev/null +++ b/gas/testsuite/gas/tic80/regops.s @@ -0,0 +1,237 @@ +;; Simple register forms +;; Those instructions which also use an immediate just use a constant. + + .text + + add r3,r4,r5 + addu r3,r4,r5 + and r5,r4,r2 + and.tt r5,r4,r2 + and.ff r10,r12,r14 + and.ft r10,r12,r14 + and.tf r10,r12,r14 + bbo r10,r8,lo.w + bbo.a r10,r8,eq.b + bbz r10,r8,ls.w + bbz.a r10,r8,hi.w + bcnd r4,r6,lt0.b + bcnd.a r4,r6,lt0.b + br r6 + br.a r6 + brcr 10 + bsr r6,r31 + bsr.a r6,r31 + cmnd r7 + cmp r3,r4,r5 + dcachec r8(r10) + dcachef r8(r10) + dld.b r4(r6),r8 + dld.h r4(r6),r8 + dld r4(r6),r8 + dld.d r4(r6),r8 + dld.ub r4(r6),r8 + dld.uh r4(r6),r8 + dst.b r4(r6),r8 + dst.h r4(r6),r8 + dst r4(r6),r8 + dst.d r4(r6),r8 + etrap r5 + exts r3,31,r5,r6 + extu r2,30,r5,r9 + fadd.sss r2,r4,r6 + fadd.ssd r2,r4,r6 + fadd.sdd r2,r4,r6 + fadd.dsd r2,r4,r6 + fadd.ddd r2,r4,r6 + fcmp.ss r4,r6,r8 + fcmp.sd r4,r6,r8 + fcmp.ds r4,r6,r8 + fcmp.dd r4,r6,r8 + fdiv.sss r2,r4,r6 + fdiv.ssd r2,r4,r6 + fdiv.sdd r2,r4,r6 + fdiv.dsd r2,r4,r6 + fdiv.ddd r2,r4,r6 + fmpy.sss r2,r4,r6 + fmpy.ssd r2,r4,r6 + fmpy.sdd r2,r4,r6 + fmpy.dsd r2,r4,r6 + fmpy.ddd r2,r4,r6 + fmpy.iii r2,r4,r6 + fmpy.uuu r2,r4,r6 + frndm.ss r4,r6 + frndm.sd r4,r6 + frndm.si r4,r6 + frndm.su r4,r6 + frndm.ds r2,r8 + frndm.dd r2,r8 + frndm.di r2,r8 + frndm.du r2,r8 + frndm.is r4,r6 + frndm.id r4,r6 + frndm.us r2,r8 + frndm.ud r2,r8 + frndn.ss r4,r6 + frndn.sd r4,r6 + frndn.si r4,r6 + frndn.su r4,r6 + frndn.ds r2,r8 + frndn.dd r2,r8 + frndn.di r2,r8 + frndn.du r2,r8 + frndn.is r4,r6 + frndn.id r4,r6 + frndn.us r2,r8 + frndn.ud r2,r8 + frndp.ss r4,r6 + frndp.sd r4,r6 + frndp.si r4,r6 + frndp.su r4,r6 + frndp.ds r2,r8 + frndp.dd r2,r8 + frndp.di r2,r8 + frndp.du r2,r8 + frndp.is r4,r6 + frndp.id r4,r6 + frndp.us r2,r8 + frndp.ud r2,r8 + frndz.ss r4,r6 + frndz.sd r4,r6 + frndz.si r4,r6 + frndz.su r4,r6 + frndz.ds r2,r8 + frndz.dd r2,r8 + frndz.di r2,r8 + frndz.du r2,r8 + frndz.is r4,r6 + frndz.id r4,r6 + frndz.us r2,r8 + frndz.ud r2,r8 + fsqrt.ss r6,r8 + fsqrt.sd r6,r8 + fsqrt.dd r6,r8 + fsub.sss r2,r4,r6 + fsub.ssd r2,r4,r6 + fsub.sdd r2,r4,r6 + fsub.dsd r2,r4,r6 + fsub.ddd r2,r4,r6 + ins r4,31,r8,r10 + jsr r4(r6),r8 + jsr.a r4(r6),r8 + ld.b r4(r6),r8 + ld.h r4(r6),r8 + ld r4(r6),r8 + ld.d r4(r6),r8 + ld.ub r4(r6),r8 + ld.uh r4(r6),r8 + lmo r7,r8 + or r1,r2,r3 + or.tt r1,r2,r3 + or.ff r1,r2,r3 + or.ft r1,r2,r3 + or.tf r1,r2,r3 + rdcr r6,r4 + rmo r4,r5 + rotl r2,31,r8,r10 + rotr r8,31,r2,r6 + shl r4,31,r2,r6 + sl.dz r4,12,r5,r6 + sl.dm r4,12,r5,r6 + sl.ds r4,12,r5,r6 + sl.ez r4,12,r5,r6 + sl.em r4,12,r5,r6 + sl.es r4,12,r5,r6 + sl.iz r4,12,r5,r6 + sl.im r4,12,r5,r6 + sli.dz r4,12,r5,r6 + sli.dm r4,12,r5,r6 + sli.ds r4,12,r5,r6 + sli.ez r4,12,r5,r6 + sli.em r4,12,r5,r6 + sli.es r4,12,r5,r6 + sli.iz r4,12,r5,r6 + sli.im r4,12,r5,r6 + sr.dz r4,12,r5,r6 + sr.dm r4,12,r5,r6 + sr.ds r4,12,r5,r6 + sr.ez r4,12,r5,r6 + sr.em r4,12,r5,r6 + sr.es r4,12,r5,r6 + sr.iz r4,12,r5,r6 + sr.im r4,12,r5,r6 + sra r4,32,r6,r8 + sri.dz r4,12,r5,r6 + sri.dm r4,12,r5,r6 + sri.ds r4,12,r5,r6 + sri.ez r4,12,r5,r6 + sri.em r4,12,r5,r6 + sri.es r4,12,r5,r6 + sri.iz r4,12,r5,r6 + sri.im r4,12,r5,r6 + srl r4,32,r6,r8 + st.b r4(r6),r8 + st.h r4(r6),r8 + st r4(r6),r8 + st.d r4(r6),r8 + sub r7,r8,r9 + subu r7,r8,r9 + swcr r8,r6,r4 + trap r10 + vadd.ss r2,r4,r4 + vadd.sd r2,r6,r6 + vadd.dd r2,r10,r10 +; vld0.s r6 +; vld1.s r7 +; vld0.d r6 +; vld1.d r8 +; vmac.sss r7,r9,0,a3 +; vmac.sss r7,r9,0,r10 +; vmac.sss r7,r9,a1,a3 +; vmac.sss r7,r9,a3,r10 +; vmac.ssd r7,r9,0,a0 +; vmac.ssd r7,r9,0,r10 +; vmac.ssd r7,r9,a1,a2 +; vmac.ssd r7,r9,a3,r10 +; vmpy.ss r1,r3,r3 +; vmpy.sd r5,r6,r6 +; vmpy.dd r2,r4,r4 +; vmsc.sss r7,r9,0,a0 +; vmsc.sss r7,r9,0,r10 +; vmsc.sss r7,r9,a0,a1 +; vmsc.sss r7,r9,a3,r10 +; vmsc.ssd r7,r9,0,a0 +; vmsc.ssd r7,r9,0,r10 +; vmsc.ssd r7,r9,a0,a1 +; vmsc.ssd r7,r9,a3,r10 +; vmsub.ss r6,a2,a4 +; vmsub.sd r6,a2,a4 +; vmsub.ss r4,a4,r6 +; vmsub.sd r4,a4,r6 +; vrnd.si r4,r6 +; vrnd.si r4,a0 +; vrnd.su r4,r6 +; vrnd.su r4,a0 +; vrnd.ss r4,r6 +; vrnd.ss r4,a0 +; vrnd.sd r4,r6 +; vrnd.sd r4,a0 +; vrnd.di r4,r6 +; vrnd.di r4,a0 +; vrnd.du r4,r6 +; vrnd.du r4,a0 +; vrnd.ds r4,r6 +; vrnd.ds r4,a0 +; vrnd.dd r4,r6 +; vrnd.dd r4,a0 +; vrnd.is r4,r6 +; vrnd.id r4,r6 +; vrnd.us r4,r6 +; vrnd.ud r4,r6 +; vst.s r6 +; vst.d r6 +; vsub.ss r2,r4,r6 +; vsub.sd r2,r4,r6 +; vsub.dd r2,r4,r6 + wrcr r6,r5 + xnor r5,r6,r7 + xor r7,r8,r9 diff --git a/gas/testsuite/gas/tic80/tic80.exp b/gas/testsuite/gas/tic80/tic80.exp new file mode 100644 index 00000000000..2d55777b346 --- /dev/null +++ b/gas/testsuite/gas/tic80/tic80.exp @@ -0,0 +1,12 @@ +# +# TI TMS320C80 tests. +# +if [istarget tic80*-*-*] then { + + run_dump_test "regops" + run_dump_test "cregops" + run_dump_test "endmask" + run_dump_test "bitnum" + run_dump_test "ccode" + run_dump_test "add" +} -- 2.30.2