From 28de9dbd2f7052e48856562bbcc67aeca6c3d04d Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 25 Apr 2023 17:52:38 +0100
Subject: [PATCH]

---
 openpower/sv/cr_int_predication.mdwn | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 865066dae..38733a22a 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -258,20 +258,15 @@ bits within the Integer element set to zero) whilst the INT (dest
 operand) elwidth field still sets the Integer element size as usual
 (8/16/32/default)
 
-**crrweird: RT, BB, fmsk.fmap**
+**sv.crrweird: RT, BB, fmsk, fmap**
 
 ```
     for i in range(VL):
-        if BB.isvec:
+        if BB.isvec: # Vector CR Field source?
             creg = CR{BB+i}
         else:
             creg = CR{BB}
-        n0 = fmsk[0] & (fmap[0] == creg[0])
-        n1 = fmsk[1] & (fmap[1] == creg[1])
-        n2 = fmsk[2] & (fmap[2] == creg[2])
-        n3 = fmsk[3] & (fmap[3] == creg[3])
-        # OR or AND to a single bit
-        n = (n0||n1||n2||n3) & fmsk
+        n = (¬fmap ^ creg) & fmsk
         result = (n != 0) if M else (n == fmsk)
         if RT.isvec:
             # TODO: RT.elwidth override to be also added here
@@ -294,7 +289,10 @@ operand) elwidth field still sets the Integer element size as usual
                 iregs[RT+i//8][0..55] = 0
                 iregs[RT+i//8][63-(i%8)] = result
         else:
+            # scalar RT destination: exceeding VL=64 is UNDEFINED
             iregs[RT][63-i] = result # results also in scalar INT
+            # only mapreduce mode (/mr) allows continuation here
+            if not SVRM.mapreduce: break
 ```
 
 Note that:
@@ -339,11 +337,7 @@ results are set to zero.
             creg = CR{BB+i}
         else:
             creg = CR{BB}
-        n0 = fmsk[0] & (fmap[0] == creg[0])
-        n1 = fmsk[1] & (fmap[1] == creg[1])
-        n2 = fmsk[2] & (fmap[2] == creg[2])
-        n3 = fmsk[3] & (fmap[3] == creg[3])
-        result = n0||n1||n2||n3 # 4-bit result
+        result = (¬fmap ^ creg) & fmsk # 4-bit result
         if RT.isvec:
             # RT.elwidth override can affect the packing
             bwid = {0b00:64, 0b01:8, 0b10:16, 0b11:32}[RT.elwidth]
@@ -363,9 +357,13 @@ results are set to zero.
                 # pack 8 results sequentially into INT registers
                 idx, boff = i//t8, i%t8
         else:
-            # exceeding VL=16 is UNDEFINED
+            # scalar RT destination: exceeding VL=16 is UNDEFINED
             idx, boff = 0, i
+        # store 4-bit result in Vector starting from RT
         iregs[RT+idx][60-boff*4:63-boff*4] = result
+        if not RT.isvec:
+            # only mapreduce mode (/mr) allows continuation here
+            if not SVRM.mapreduce: break
 ```
 
 # Predication Examples
-- 
2.30.2