From 28eff03dbc3202a06bdfaa54910e89e02fbf1cf5 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 3 Jun 2020 17:26:04 -0700
Subject: [PATCH] move mulAddRecFN.py and nmigen_div_experiment.py to unused
 dir

---
 src/ieee754/unused/__init__.py                          | 0
 src/ieee754/unused/fpdiv/__init__.py                    | 0
 src/ieee754/{ => unused}/fpdiv/mulAddRecFN.py           | 0
 src/ieee754/{ => unused}/fpdiv/nmigen_div_experiment.py | 0
 src/ieee754/unused/fpdiv/test/__init__.py               | 0
 src/ieee754/{ => unused}/fpdiv/test/test_div.py         | 6 +++---
 src/ieee754/{ => unused}/fpdiv/test/test_div64.py       | 6 +++---
 7 files changed, 6 insertions(+), 6 deletions(-)
 create mode 100644 src/ieee754/unused/__init__.py
 create mode 100644 src/ieee754/unused/fpdiv/__init__.py
 rename src/ieee754/{ => unused}/fpdiv/mulAddRecFN.py (100%)
 rename src/ieee754/{ => unused}/fpdiv/nmigen_div_experiment.py (100%)
 create mode 100644 src/ieee754/unused/fpdiv/test/__init__.py
 rename src/ieee754/{ => unused}/fpdiv/test/test_div.py (92%)
 rename src/ieee754/{ => unused}/fpdiv/test/test_div64.py (89%)

diff --git a/src/ieee754/unused/__init__.py b/src/ieee754/unused/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/src/ieee754/unused/fpdiv/__init__.py b/src/ieee754/unused/fpdiv/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/src/ieee754/fpdiv/mulAddRecFN.py b/src/ieee754/unused/fpdiv/mulAddRecFN.py
similarity index 100%
rename from src/ieee754/fpdiv/mulAddRecFN.py
rename to src/ieee754/unused/fpdiv/mulAddRecFN.py
diff --git a/src/ieee754/fpdiv/nmigen_div_experiment.py b/src/ieee754/unused/fpdiv/nmigen_div_experiment.py
similarity index 100%
rename from src/ieee754/fpdiv/nmigen_div_experiment.py
rename to src/ieee754/unused/fpdiv/nmigen_div_experiment.py
diff --git a/src/ieee754/unused/fpdiv/test/__init__.py b/src/ieee754/unused/fpdiv/test/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/src/ieee754/fpdiv/test/test_div.py b/src/ieee754/unused/fpdiv/test/test_div.py
similarity index 92%
rename from src/ieee754/fpdiv/test/test_div.py
rename to src/ieee754/unused/fpdiv/test/test_div.py
index 0670900b..35caeb72 100644
--- a/src/ieee754/fpdiv/test/test_div.py
+++ b/src/ieee754/unused/fpdiv/test/test_div.py
@@ -6,7 +6,7 @@ from operator import truediv
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from ieee754.fpdiv.nmigen_div_experiment import FPDIV
+from ieee754.unused.fpdiv.nmigen_div_experiment import FPDIV
 
 from ieee754.fpcommon.test.unit_test_single import (get_mantissa,
                                 get_exponent, get_sign, is_nan,
@@ -15,7 +15,7 @@ from ieee754.fpcommon.test.unit_test_single import (get_mantissa,
                                 run_edge_cases, run_corner_cases)
 
 
-def testbench(dut):
+def tstbench(dut):
     yield from check_case(dut, 0x80000000, 0x00000000, 0xffc00000)
     yield from check_case(dut, 0x00000000, 0x80000000, 0xffc00000)
     yield from check_case(dut, 0x0002b017, 0xff3807ab, 0x80000000)
@@ -44,5 +44,5 @@ def testbench(dut):
 
 if __name__ == '__main__':
     dut = FPDIV(width=32)
-    run_simulation(dut, testbench(dut), vcd_name="test_div.vcd")
+    run_simulation(dut, tstbench(dut), vcd_name="test_div.vcd")
 
diff --git a/src/ieee754/fpdiv/test/test_div64.py b/src/ieee754/unused/fpdiv/test/test_div64.py
similarity index 89%
rename from src/ieee754/fpdiv/test/test_div64.py
rename to src/ieee754/unused/fpdiv/test/test_div64.py
index 16162445..e3c812fe 100644
--- a/src/ieee754/fpdiv/test/test_div64.py
+++ b/src/ieee754/unused/fpdiv/test/test_div64.py
@@ -2,7 +2,7 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from operator import truediv
 
-from ieee754.fpdiv.nmigen_div_experiment import FPDIV
+from ieee754.unused.fpdiv.nmigen_div_experiment import FPDIV
 
 from ieee754.fpcommon.test.unit_test_double import (get_mantissa,
                                 get_exponent, get_sign, is_nan,
@@ -10,7 +10,7 @@ from ieee754.fpcommon.test.unit_test_double import (get_mantissa,
                                 match, get_case, check_case, run_fpunit,
                                 run_edge_cases, run_corner_cases)
 
-def testbench(dut):
+def tstbench(dut):
     yield from check_case(dut, 0x4008000000000000, 0x3FF0000000000000,
                                0x4008000000000000)
     yield from check_case(dut, 0x3FF0000000000000, 0x4008000000000000,
@@ -31,5 +31,5 @@ def testbench(dut):
 
 if __name__ == '__main__':
     dut = FPDIV(width=64)
-    run_simulation(dut, testbench(dut), vcd_name="test_div64.vcd")
+    run_simulation(dut, tstbench(dut), vcd_name="test_div64.vcd")
 
-- 
2.30.2