From 28f00c3a9adc778ddd1b7daeb29fd87ff50e4ae2 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 27 Jan 2012 22:09:03 +0100
Subject: [PATCH] Add on-chip SRAM

---
 milkymist/sram/__init__.py | 27 +++++++++++++++++++++++++++
 top.py                     |  6 ++++--
 2 files changed, 31 insertions(+), 2 deletions(-)
 create mode 100644 milkymist/sram/__init__.py

diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py
new file mode 100644
index 00000000..5071c423
--- /dev/null
+++ b/milkymist/sram/__init__.py
@@ -0,0 +1,27 @@
+from migen.fhdl.structure import *
+from migen.bus import wishbone
+
+class SRAM:
+	def __init__(self, depth):
+		self.bus = wishbone.Slave("sram")
+		self.depth = depth
+	
+	def get_fragment(self):
+		# generate write enable signal
+		we = Signal(BV(4))
+		comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.sel_i[3-i])
+			for i in range(4)]
+		# split address
+		nbits = bits_for(self.depth-1)
+		partial_adr = Signal(BV(nbits))
+		comb.append(partial_adr.eq(self.bus.adr_i[:nbits]))
+		# generate ack
+		sync = [
+			self.bus.ack_o.eq(0),
+			If(self.bus.cyc_i & self.bus.stb_i & ~self.bus.ack_o,
+				self.bus.ack_o.eq(1)
+			)
+		]
+		# memory
+		port = MemoryPort(partial_adr, self.bus.dat_o, we, self.bus.dat_i, we_granularity=8)
+		return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])
diff --git a/top.py b/top.py
index a2097b81..60ed107a 100644
--- a/top.py
+++ b/top.py
@@ -2,22 +2,24 @@ from migen.fhdl.structure import *
 from migen.fhdl import tools, verilog, autofragment
 from migen.bus import wishbone, csr, wishbone2csr
 
-from milkymist import m1reset, clkfx, lm32, norflash, uart
+from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
 import constraints
 
 def get():
 	MHz = 1000000
 	clk_freq = 80*MHz
+	sram_size = 4096 # in kilobytes
 	
 	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
 	reset0 = m1reset.M1Reset()
 	
 	cpu0 = lm32.LM32()
 	norflash0 = norflash.NorFlash(25, 12)
+	sram0 = sram.SRAM(sram_size//4)
 	wishbone2csr0 = wishbone2csr.WB2CSR()
 	wishbonecon0 = wishbone.InterconnectShared(
 		[cpu0.ibus, cpu0.dbus],
-		[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
+		[(0, norflash0.bus), (1, sram0.bus), (3, wishbone2csr0.wishbone)],
 		register=True,
 		offset=1)
 	uart0 = uart.UART(0, clk_freq, baud=115200)
-- 
2.30.2