From 28fab4295e9631ca91c5ebdf26d1bee23011d57e Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 14 Aug 2012 15:45:52 -0700 Subject: [PATCH] i965: Un-hardcode WM binding table from update_texture_surface. Currently, we mirror the VS and WM binding tables' texture entries. That may not continue to be true, so in preparation, pass in the binding table and surface index as arguments. Signed-off-by: Kenneth Graunke Reviewed-by: Paul Berry Reviewed-by: Eric Anholt --- .../drivers/dri/i965/brw_wm_surface_state.c | 24 +++++++++++-------- .../drivers/dri/i965/gen7_wm_surface_state.c | 22 ++++++++++------- src/mesa/drivers/dri/intel/intel_context.h | 5 +++- 3 files changed, 31 insertions(+), 20 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 220af1bf9d5..0c87b841d71 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -654,12 +654,14 @@ brw_get_surface_num_multisamples(unsigned num_samples) static void -brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) +brw_update_buffer_texture_surface(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index) { struct brw_context *brw = brw_context(ctx); struct intel_context *intel = &brw->intel; struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; - const GLuint surf_index = SURF_INDEX_TEXTURE(unit); uint32_t *surf; struct intel_buffer_object *intel_obj = intel_buffer_object(tObj->BufferObject); @@ -674,7 +676,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) } surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - 6 * 4, 32, &brw->wm.surf_offset[surf_index]); + 6 * 4, 32, &binding_table[surf_index]); surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT)); @@ -687,7 +689,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) /* Emit relocation to surface contents. */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, - brw->wm.surf_offset[surf_index] + 4, + binding_table[surf_index] + 4, bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); int w = intel_obj->Base.Size / texel_size; @@ -706,7 +708,10 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) } static void -brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) +brw_update_texture_surface(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index) { struct brw_context *brw = brw_context(ctx); struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; @@ -714,19 +719,18 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) struct intel_mipmap_tree *mt = intelObj->mt; struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); - const GLuint surf_index = SURF_INDEX_TEXTURE(unit); uint32_t *surf; int width, height, depth; if (tObj->Target == GL_TEXTURE_BUFFER) { - brw_update_buffer_texture_surface(ctx, unit); + brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); return; } intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth); surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - 6 * 4, 32, &brw->wm.surf_offset[surf_index]); + 6 * 4, 32, &binding_table[surf_index]); surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT | BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | @@ -754,7 +758,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, - brw->wm.surf_offset[surf_index] + 4, + binding_table[surf_index] + 4, intelObj->mt->region->bo, intelObj->mt->offset, I915_GEM_DOMAIN_SAMPLER, 0); @@ -1242,7 +1246,7 @@ brw_update_texture_surfaces(struct brw_context *brw) /* _NEW_TEXTURE */ if (texUnit->_ReallyEnabled) { - brw->intel.vtbl.update_texture_surface(ctx, i); + brw->intel.vtbl.update_texture_surface(ctx, i, brw->wm.surf_offset, surf); } else { brw->wm.surf_offset[surf] = 0; } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index e0fd3906250..97ae0e2f9a4 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -203,11 +203,13 @@ gen7_check_surface_setup(struct gen7_surface_state *surf, static void -gen7_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) +gen7_update_buffer_texture_surface(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index) { struct brw_context *brw = brw_context(ctx); struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; - const GLuint surf_index = SURF_INDEX_TEXTURE(unit); struct gen7_surface_state *surf; struct intel_buffer_object *intel_obj = intel_buffer_object(tObj->BufferObject); @@ -216,7 +218,7 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) int texel_size = _mesa_get_format_bytes(format); surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]); + sizeof(*surf), 32, &binding_table[surf_index]); memset(surf, 0, sizeof(*surf)); surf->ss0.surface_type = BRW_SURFACE_BUFFER; @@ -237,7 +239,7 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) * a separate cache and is just the sampler cache. */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, - (brw->wm.surf_offset[surf_index] + + (binding_table[surf_index] + offsetof(struct gen7_surface_state, ss1)), bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); @@ -261,7 +263,10 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) } static void -gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) +gen7_update_texture_surface(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index) { struct brw_context *brw = brw_context(ctx); struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; @@ -269,12 +274,11 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) struct intel_mipmap_tree *mt = intelObj->mt; struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); - const GLuint surf_index = SURF_INDEX_TEXTURE(unit); struct gen7_surface_state *surf; int width, height, depth; if (tObj->Target == GL_TEXTURE_BUFFER) { - gen7_update_buffer_texture_surface(ctx, unit); + gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); return; } @@ -285,7 +289,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth); surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]); + sizeof(*surf), 32, &binding_table[surf_index]); memset(surf, 0, sizeof(*surf)); if (mt->align_h == 4) @@ -347,7 +351,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, - brw->wm.surf_offset[surf_index] + + binding_table[surf_index] + offsetof(struct gen7_surface_state, ss1), intelObj->mt->region->bo, intelObj->mt->offset, I915_GEM_DOMAIN_SAMPLER, 0); diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 5075601d587..ce8cf48eee6 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -189,7 +189,10 @@ struct intel_context * Surface state operations (i965+ only) * \{ */ - void (*update_texture_surface)(struct gl_context *ctx, unsigned unit); + void (*update_texture_surface)(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index); void (*update_renderbuffer_surface)(struct brw_context *brw, struct gl_renderbuffer *rb, unsigned unit); -- 2.30.2