From 28fbcac967d6c2a0085faa2007c98d64d3203491 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 11 Aug 2017 12:55:25 -0700 Subject: [PATCH] Make pylint happy. --- debug/targets/RISC-V/spike32-2.py | 2 +- debug/targets/RISC-V/spike64-2.py | 2 +- debug/targets/SiFive/Freedom/U500Sim.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 3f87d26..09bab1d 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -1,7 +1,7 @@ import targets import testlib -import spike32 +import spike32 # pylint: disable=import-error class spike32_2(targets.Target): harts = [spike32.spike32_hart(), spike32.spike32_hart()] diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index e1df6d2..f2e0a8a 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -1,7 +1,7 @@ import targets import testlib -import spike64 +import spike64 # pylint: disable=import-error class spike64_2(targets.Target): harts = [spike64.spike64_hart(), spike64.spike64_hart()] diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py index 5c500c4..065ab08 100644 --- a/debug/targets/SiFive/Freedom/U500Sim.py +++ b/debug/targets/SiFive/Freedom/U500Sim.py @@ -8,7 +8,7 @@ class U500Hart(targets.Hart): instruction_hardware_breakpoint_count = 2 link_script_path = "Freedom.lds" -class U500Sim(Target): +class U500Sim(targets.Target): timeout_sec = 6000 openocd_config_path = "Freedom.cfg" harts = [U500Hart()] -- 2.30.2