From 2904acd9383e9aae08ebb139d882a47511f1d401 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 15 Jun 2020 19:23:32 -0400 Subject: [PATCH] pan/mdg: Schedule writeout to VLUT MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Many thanks to Icecream95 for noticing this is possible if alpha is not written. total instructions in shared programs: 50509 -> 50508 (<.01%) instructions in affected programs: 221 -> 220 (-0.45%) helped: 2 HURT: 1 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.74% max: 1.35% x̄: 1.04% x̃: 1.04% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 9.09% max: 9.09% x̄: 9.09% x̃: 9.09% total bundles in shared programs: 25675 -> 25640 (-0.14%) bundles in affected programs: 5434 -> 5399 (-0.64%) helped: 34 HURT: 0 helped stats (abs) min: 1 max: 2 x̄: 1.03 x̃: 1 helped stats (rel) min: 0.27% max: 20.00% x̄: 2.29% x̃: 0.67% 95% mean confidence interval for bundles value: -1.09 -0.97 95% mean confidence interval for bundles %-change: -3.64% -0.94% Bundles are helped. total quadwords in shared programs: 40887 -> 40899 (0.03%) quadwords in affected programs: 1995 -> 2007 (0.60%) helped: 2 HURT: 16 helped stats (abs) min: 1 max: 3 x̄: 2.00 x̃: 2 helped stats (rel) min: 1.67% max: 2.40% x̄: 2.03% x̃: 2.03% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.54% max: 5.88% x̄: 1.40% x̃: 0.86% 95% mean confidence interval for quadwords value: 0.15 1.18 95% mean confidence interval for quadwords %-change: 0.13% 1.90% Quadwords are HURT. total registers in shared programs: 3916 -> 3917 (0.03%) registers in affected programs: 2 -> 3 (50.00%) helped: 0 HURT: 1 total threads in shared programs: 2455 -> 2455 (0.00%) threads in affected programs: 0 -> 0 helped: 0 HURT: 0 Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/midgard/midgard_schedule.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index 7ebcc2d4ebb..abaf3ed578e 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -334,10 +334,11 @@ struct midgard_predicate { * scheduled one). Excludes conditional branches and csel */ bool no_cond; - /* Require a minimal mask and (if nonzero) given destination. Used for - * writeout optimizations */ + /* Require (or reject) a minimal mask and (if nonzero) given + * destination. Used for writeout optimizations */ unsigned mask; + unsigned no_mask; unsigned dest; /* For load/store: how many pipeline registers are in use? The two @@ -631,6 +632,9 @@ mir_choose_instruction( if (mask && ((~instructions[i]->mask) & mask)) continue; + if (instructions[i]->mask & predicate->no_mask) + continue; + if (ldst && mir_pipeline_count(instructions[i]) + predicate->pipeline_count > 2) continue; @@ -1003,9 +1007,11 @@ mir_schedule_alu( if (writeout < PAN_WRITEOUT_Z) mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL); - if (!writeout) { - mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT); - } else { + predicate.no_mask = writeout ? (1 << 3) : 0; + mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT); + predicate.no_mask = 0; + + if (writeout) { /* Propagate up */ bundle.last_writeout = branch->last_writeout; } @@ -1124,7 +1130,7 @@ mir_schedule_alu( /* Check if writeout reads its own register */ if (writeout) { - midgard_instruction *stages[] = { sadd, vadd, smul }; + midgard_instruction *stages[] = { sadd, vadd, smul, vlut }; unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0]; unsigned writeout_mask = 0x0; bool bad_writeout = false; -- 2.30.2