From 290f819a515b7b6586a83a549c0969f3d4fb7663 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 01:58:36 +0100 Subject: [PATCH] add some more constants and ref to POWER9 pdf --- src/soc/fu/trap/main_stage.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 7d585a2d..9c6ee0e1 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -16,12 +16,18 @@ from soc.decoder.power_fieldsn import SignalBitRange # TODO at some point move these to their own module (for use elsewhere) """ + Listed in V3.0B Book III Chap 4.2.1 -- MSR bit numbers constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode + constant MSR_HV : integer := (63 - 3); -- Hypervisor state + constant MSR_S : integer := (63 - 41); -- Secure state constant MSR_EE : integer := (63 - 48); -- External interrupt Enable constant MSR_PR : integer := (63 - 49); -- PRoblem state + constant MSR_FP : integer := (63 - 50); -- FP available + constant MSR_ME : integer := (63 - 51); -- Machine Check int enable constant MSR_IR : integer := (63 - 58); -- Instruction Relocation constant MSR_DR : integer := (63 - 59); -- Data Relocation + constant MSR_PMM : integer := (63 - 60); -- Performance Monitor Mark constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt constant MSR_LE : integer := (63 - 63); -- Little Endian """ -- 2.30.2