From 291c2798103999b66f9ad5b9a885a67f3ef2160e Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 18 Apr 2018 10:31:44 +0100 Subject: [PATCH] arch-arm: Change disassemble when MSR to UNKNOWN register This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg --- src/arch/arm/isa/formats/aarch64.isa | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 7752ba08f..00bd0770f 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -369,7 +369,14 @@ namespace Aarch64 } // Check for invalid registers if (miscReg == MISCREG_UNKNOWN) { - return new Unknown64(machInst); + auto full_mnemonic = + csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", + read ? "mrs" : "msr", + op0, op1, crn, crm, op2); + + return new FailUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic); + } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { if (read) -- 2.30.2