From 291cc0665e3d62f8b7a284b0e54d0684ff6f2621 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 30 Jan 2019 12:00:21 +0000 Subject: [PATCH] arch-arm: Move GICv3 detection at startup time At the moment the haveGicV3 parameter is used only to signal its presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends on the system->getGIC pointing to a GICv3 model. However this pointer is set in the System only at init time (after construction), which means that the haveGICv3CPUInterface will always be false. This patch is fixing this by moving the parameter initialization at startup time, together with the cpu interface registration. Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421 Signed-off-by: Giacomo Travaglini Reviewed-by: Anouk Van Laer Reviewed-on: https://gem5-review.googlesource.com/c/16483 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 97de97e6e..3b10f68a4 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -64,6 +64,7 @@ ISA::ISA(Params *p) _decoderFlavour(p->decoderFlavour), _vecRegRenameMode(Enums::Full), pmu(p->pmu), + haveGICv3CPUInterface(false), impdefAsNop(p->impdef_nop) { miscRegs[MISCREG_SCTLR_RST] = 0; @@ -96,13 +97,6 @@ ISA::ISA(Params *p) physAddrRange = 32; // dummy value } - // GICv3 CPU interface system registers are supported - haveGICv3CPUInterface = false; - - if (system && dynamic_cast(system->getGIC())) { - haveGICv3CPUInterface = true; - } - // Initial rename mode depends on highestEL const_cast(_vecRegRenameMode) = highestELIs64 ? Enums::Full : Enums::Elem; @@ -388,6 +382,7 @@ ISA::startup(ThreadContext *tc) if (system) { Gicv3 *gicv3 = dynamic_cast(system->getGIC()); if (gicv3) { + haveGICv3CPUInterface = true; gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); gicv3CpuInterface->setISA(this); } -- 2.30.2