From 292139066698216dfc8fb1a65d327bb063d16a00 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 4 Jul 2013 11:26:54 -0700 Subject: [PATCH] i965: Replace intel_context:needs_ff_sync with intel->gen == 5. Technically, needs_ff_sync was set on Gen5+, but it was only consulted in the clipper threads and quad/lineloop decomposition code, which are both Gen4-5 only. So in reality it only identified Ironlake. The named flag doesn't really clarify things, and seems like overkill. Signed-off-by: Kenneth Graunke Acked-by: Chris Forbes Acked-by: Paul Berry Acked-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_clip_line.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_tri.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_util.c | 4 ++-- src/mesa/drivers/dri/i965/brw_gs_emit.c | 9 ++++----- src/mesa/drivers/dri/i965/intel_context.c | 4 ---- src/mesa/drivers/dri/i965/intel_context.h | 1 - 6 files changed, 8 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 508fa29091f..f7c8d099a54 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -85,7 +85,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) i++; } - if (intel->needs_ff_sync) { + if (intel->gen == 5) { c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; } diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index b2062d46c0b..72de3043476 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -122,7 +122,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; - if (intel->needs_ff_sync) { + if (intel->gen == 5) { c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; } diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index cefffe69120..8d90017b046 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -364,7 +364,7 @@ void brw_clip_ff_sync(struct brw_clip_compile *c) { struct intel_context *intel = &c->func.brw->intel; - if (intel->needs_ff_sync) { + if (intel->gen == 5) { struct brw_compile *p = &c->func; brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); @@ -389,7 +389,7 @@ void brw_clip_init_ff_sync(struct brw_clip_compile *c) { struct intel_context *intel = &c->func.brw->intel; - if (intel->needs_ff_sync) { + if (intel->gen == 5) { struct brw_compile *p = &c->func; brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0)); diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index cbfc6aab2e4..e85dcc190c9 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -203,8 +203,7 @@ static void brw_gs_emit_vue(struct brw_gs_compile *c, /** * Send an FF_SYNC message to ensure that all previously spawned GS threads * have finished sending primitives down the pipeline, and to allocate a URB - * entry for the first output vertex. Only needed when intel->needs_ff_sync - * is true. + * entry for the first output vertex. Only needed on Ironlake+. * * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to @@ -237,7 +236,7 @@ void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) /* Use polygons for correct edgeflag behaviour. Note that vertex 3 * is the PV for quads, but vertex 0 for polygons: */ - if (intel->needs_ff_sync) + if (intel->gen == 5) brw_gs_ff_sync(c, 1); brw_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) @@ -273,7 +272,7 @@ void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) brw_gs_alloc_regs(c, 4, false); brw_gs_initialize_header(c); - if (intel->needs_ff_sync) + if (intel->gen == 5) brw_gs_ff_sync(c, 1); brw_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) @@ -309,7 +308,7 @@ void brw_gs_lines( struct brw_gs_compile *c ) brw_gs_alloc_regs(c, 2, false); brw_gs_initialize_header(c); - if (intel->needs_ff_sync) + if (intel->gen == 5) brw_gs_ff_sync(c, 1); brw_gs_overwrite_header_dw2( c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index e4d7bd50bc8..53aa19c5cf3 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -495,10 +495,6 @@ intelInitContext(struct intel_context *intel, intel->is_g4x = true; } - if (intel->gen >= 5) { - intel->needs_ff_sync = true; - } - intel->has_separate_stencil = intel->intelScreen->hw_has_separate_stencil; intel->must_use_separate_stencil = intel->intelScreen->hw_must_use_separate_stencil; intel->has_hiz = intel->gen >= 6; diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index a55572307ec..9be7fc8a38c 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -161,7 +161,6 @@ struct intel_context */ int gen; int gt; - bool needs_ff_sync; bool is_haswell; bool is_baytrail; bool is_g4x; -- 2.30.2