From 292df1940126f267418e656b9ec33eb3f06667b8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 13 Nov 2015 14:55:50 -0800 Subject: [PATCH] i965: Set MaxCombinedUniformBlocks properly. Up until now, we've been letting core Mesa initialize it to 36 for us (which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)). With compute and tessellation, we need to increase this. Signed-off-by: Kenneth Graunke Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index e70ad982f48..2ea0a9eca92 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -391,6 +391,7 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits); ctx->Const.MaxUniformBufferBindings = num_stages * BRW_MAX_UBO; + ctx->Const.MaxCombinedUniformBlocks = num_stages * BRW_MAX_UBO; ctx->Const.MaxCombinedAtomicBuffers = num_stages * BRW_MAX_ABO; ctx->Const.MaxCombinedShaderStorageBlocks = num_stages * BRW_MAX_SSBO; ctx->Const.MaxShaderStorageBufferBindings = num_stages * BRW_MAX_SSBO; -- 2.30.2