From 294855e29287cd35705fe67e540d9ee917d09982 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Nov 2014 10:19:24 +0100 Subject: [PATCH] phy: use primitives dict and use only sata.std --- lib/sata/phy/k7sataphy/crg.py | 4 ++-- lib/sata/phy/k7sataphy/ctrl.py | 12 +++++------ lib/sata/phy/k7sataphy/datapath.py | 4 ++-- lib/sata/phy/k7sataphy/gtx.py | 2 +- lib/sata/phy/k7sataphy/std.py | 8 -------- lib/sata/std.py | 32 ++++++++++++++++++------------ 6 files changed, 30 insertions(+), 32 deletions(-) delete mode 100644 lib/sata/phy/k7sataphy/std.py diff --git a/lib/sata/phy/k7sataphy/crg.py b/lib/sata/phy/k7sataphy/crg.py index 93ac490a..aae3a938 100644 --- a/lib/sata/phy/k7sataphy/crg.py +++ b/lib/sata/phy/k7sataphy/crg.py @@ -4,7 +4,7 @@ from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.fsm import FSM, NextState -from lib.sata.k7sataphy.std import * +from lib.sata.std import * from lib.sata.k7sataphy.gtx import GTXE2_COMMON class K7SATAPHYCRG(Module): @@ -58,7 +58,7 @@ class K7SATAPHYCRG(Module): p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked, # DRP - i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=, + i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=, i_DADDR=0, i_DI=0, #o_DO=, # VCO diff --git a/lib/sata/phy/k7sataphy/ctrl.py b/lib/sata/phy/k7sataphy/ctrl.py index c4ffb463..3c840d06 100644 --- a/lib/sata/phy/k7sataphy/ctrl.py +++ b/lib/sata/phy/k7sataphy/ctrl.py @@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.fsm import FSM, NextState from migen.flow.actor import Sink, Source -from lib.sata.k7sataphy.std import * +from lib.sata.std import * def us(t, clk_freq): clk_period_us = 1000000/clk_freq @@ -117,7 +117,7 @@ class K7SATAPHYHostCtrl(Module): ) fsm.act("SEND_ALIGN", gtx.txelecidle.eq(0), - self.source.data.eq(ALIGN_VAL), + self.source.data.eq(primitives["ALIGN"]), self.source.charisk.eq(0b0001), If(non_align_cnt == 3, NextState("READY") @@ -125,7 +125,7 @@ class K7SATAPHYHostCtrl(Module): ) fsm.act("READY", gtx.txelecidle.eq(0), - self.source.data.eq(SYNC_VAL), + self.source.data.eq(primitives["SYNC"]), self.source.charisk.eq(0b0001), self.ready.eq(1), ) @@ -139,7 +139,7 @@ class K7SATAPHYHostCtrl(Module): gtx.txcomwake.eq(txcomwake & ~txcomwake_d), ] - self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL)); + self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"])); self.sync += \ If(fsm.ongoing("RESET"), align_timeout_cnt.eq(us(873, clk_freq)) @@ -254,7 +254,7 @@ class K7SATAPHYDeviceCtrl(Module): fsm.act("SEND_ALIGN", gtx.txelecidle.eq(0), gtx.rxalign.eq(1), - self.source.data.eq(ALIGN_VAL), + self.source.data.eq(primitives["ALIGN"]), self.source.charisk.eq(0b0001), If(align_detect, NextState("READY") @@ -284,7 +284,7 @@ class K7SATAPHYDeviceCtrl(Module): gtx.txcomwake.eq(txcomwake & ~txcomwake_d), ] - self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL)); + self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"])); self.sync += \ If(fsm.ongoing("RESET"), align_timeout_cnt.eq(us(55, clk_freq)) diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py index 83088d99..bd4b6670 100644 --- a/lib/sata/phy/k7sataphy/datapath.py +++ b/lib/sata/phy/k7sataphy/datapath.py @@ -3,7 +3,7 @@ from migen.genlib.misc import chooser from migen.actorlib.fifo import AsyncFIFO from migen.flow.actor import Sink, Source -from lib.sata.k7sataphy.std import * +from lib.sata.std import * class K7SATAPHYDatapathRX(Module): def __init__(self): @@ -143,7 +143,7 @@ class K7SATAPHYDatapath(Module): If(ctrl.ready, If(send_align, tx.sink.stb.eq(1), - tx.sink.data.eq(ALIGN_VAL), + tx.sink.data.eq(primitives["ALIGN"]), tx.sink.charisk.eq(0b0001), self.sink.ack.eq(0) ).Else( diff --git a/lib/sata/phy/k7sataphy/gtx.py b/lib/sata/phy/k7sataphy/gtx.py index 982cbb9a..10130313 100644 --- a/lib/sata/phy/k7sataphy/gtx.py +++ b/lib/sata/phy/k7sataphy/gtx.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.genlib.cdc import * -from lib.sata.k7sataphy.std import * +from lib.sata.std import * class _PulseSynchronizer(PulseSynchronizer): def __init__(self, i, idomain, o, odomain): diff --git a/lib/sata/phy/k7sataphy/std.py b/lib/sata/phy/k7sataphy/std.py deleted file mode 100644 index 5a218990..00000000 --- a/lib/sata/phy/k7sataphy/std.py +++ /dev/null @@ -1,8 +0,0 @@ -from migen.fhdl.std import * -from migen.genlib.record import * - -ALIGN_VAL = 0x7B4A4ABC -SYNC_VAL = 0xB5B5957C - -def ones(width): - return 2**width-1 diff --git a/lib/sata/std.py b/lib/sata/std.py index b2370c50..7979b38a 100644 --- a/lib/sata/std.py +++ b/lib/sata/std.py @@ -1,18 +1,24 @@ from migen.fhdl.std import * +from migen.genlib.record import * -ALIGN_VAL = 0x7B4A4ABC -SYNC_VAL = 0xB5B5957C -R_RDY_VAL = 0x4A4A957C -R_OK_VAL = 0x3535B57C -R_ERR_VAL = 0x5656B57C -R_IP_VAL = 0X5555B57C -X_RDY_VAL = 0x5757B57C -CONT_VAL = 0x9999AA7C -WTRM_VAL = 0x5858B57C -SOF_VAL = 0x3737B57C -EOF_VAL = 0xD5D5B57C -HOLD_VAL = 0xD5D5AA7C -HOLD_ACK = 0X9595AA7C +primitives = { + "ALIGN" : 0x7B4A4ABC, + "SYNC" : 0xB5B5957C, + "R_RDY" : 0x4A4A957C, + "R_OK" : 0x3535B57C, + "R_ERR" : 0x5656B57C, + "R_IP" : 0X5555B57C, + "X_RDY" : 0x5757B57C, + "CONT" : 0x9999AA7C, + "WTRM" : 0x5858B57C, + "SOF" : 0x3737B57C, + "EOF" : 0xD5D5B57C, + "HOLD" : 0xD5D5AA7C, + "HOLD" : 0X9595AA7C +} + +def ones(width): + return 2**width-1 def phy_layout(dw): layout = [ -- 2.30.2