From 2948f6a16a36a95ab578610d5b2fb83f5d7d2bf2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 9 Jun 2013 14:17:30 +0200 Subject: [PATCH] examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI --- examples/sim/abstract_transactions.py | 111 ----------------------- examples/sim/abstract_transactions_wb.py | 89 ++++++++++++++++++ 2 files changed, 89 insertions(+), 111 deletions(-) delete mode 100644 examples/sim/abstract_transactions.py create mode 100644 examples/sim/abstract_transactions_wb.py diff --git a/examples/sim/abstract_transactions.py b/examples/sim/abstract_transactions.py deleted file mode 100644 index 0922d04a..00000000 --- a/examples/sim/abstract_transactions.py +++ /dev/null @@ -1,111 +0,0 @@ -from random import Random - -from migen.fhdl.std import * -from migen.bus.transactions import * -from migen.bus import wishbone, asmibus -from migen.sim.generic import Simulator - -# Our bus master. -# Python generators let us program bus transactions in an elegant sequential style. -def my_generator(): - prng = Random(92837) - - # Write to the first addresses. - for x in range(10): - t = TWrite(x, 2*x) - yield t - print("Wrote in " + str(t.latency) + " cycle(s)") - # Insert some dead cycles to simulate bus inactivity. - for delay in range(prng.randrange(0, 3)): - yield None - - # Read from the first addresses. - for x in range(10): - t = TRead(x) - yield t - print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)") - for delay in range(prng.randrange(0, 3)): - yield None - -# Our bus slave. -class MyModel: - def read(self, address): - return address + 4 - -class MyModelWB(MyModel, wishbone.TargetModel): - def __init__(self): - self.prng = Random(763627) - - def can_ack(self, bus): - # Simulate variable latency. - return self.prng.randrange(0, 2) - -class MyModelASMI(MyModel, asmibus.TargetModel): - pass - -def test_wishbone(): - print("*** Wishbone test") - - # The "wishbone.Initiator" library component runs our generator - # and manipulates the bus signals accordingly. - master = wishbone.Initiator(my_generator()) - # The "wishbone.Target" library component examines the bus signals - # and calls into our model object. - slave = wishbone.Target(MyModelWB()) - # The "wishbone.Tap" library component examines the bus at the slave port - # and displays the transactions on the console (/). - tap = wishbone.Tap(slave.bus) - # Connect the master to the slave. - intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus) - # A small extra simulation function to terminate the process when - # the initiator is done (i.e. our generator is exhausted). - def end_simulation(s): - s.interrupt = master.done - fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) - sim = Simulator(fragment) - sim.run() - -def test_asmi(): - print("*** ASMI test") - - # Create a hub with one port for our initiator. - hub = asmibus.Hub(32, 32) - port = hub.get_port() - hub.finalize() - # Create the initiator, target and tap (similar to the Wishbone case). - master = asmibus.Initiator(my_generator(), port) - slave = asmibus.Target(MyModelASMI(), hub) - tap = asmibus.Tap(hub) - # Run the simulation (same as the Wishbone case). - def end_simulation(s): - s.interrupt = master.done - fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) - sim = Simulator(fragment) - sim.run() - -test_wishbone() -test_asmi() - -# Output: -# -# Wrote in 0 cycle(s) -# -# Wrote in 0 cycle(s) -# -# Wrote in 0 cycle(s) -# -# Wrote in 1 cycle(s) -# -# Wrote in 1 cycle(s) -# -# Wrote in 2 cycle(s) -# ... -# -# Read 4 in 2 cycle(s) -# -# Read 5 in 2 cycle(s) -# -# Read 6 in 1 cycle(s) -# -# Read 7 in 1 cycle(s) -# ... diff --git a/examples/sim/abstract_transactions_wb.py b/examples/sim/abstract_transactions_wb.py new file mode 100644 index 00000000..813772eb --- /dev/null +++ b/examples/sim/abstract_transactions_wb.py @@ -0,0 +1,89 @@ +from random import Random + +from migen.fhdl.std import * +from migen.bus.transactions import * +from migen.bus import wishbone +from migen.sim.generic import Simulator + +# Our bus master. +# Python generators let us program bus transactions in an elegant sequential style. +def my_generator(): + prng = Random(92837) + + # Write to the first addresses. + for x in range(10): + t = TWrite(x, 2*x) + yield t + print("Wrote in " + str(t.latency) + " cycle(s)") + # Insert some dead cycles to simulate bus inactivity. + for delay in range(prng.randrange(0, 3)): + yield None + + # Read from the first addresses. + for x in range(10): + t = TRead(x) + yield t + print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)") + for delay in range(prng.randrange(0, 3)): + yield None + +# Our bus slave. +class MyModelWB(wishbone.TargetModel): + def __init__(self): + self.prng = Random(763627) + + def read(self, address): + return address + 4 + + def can_ack(self, bus): + # Simulate variable latency. + return self.prng.randrange(0, 2) + +class TB(Module): + def __init__(self): + # The "wishbone.Initiator" library component runs our generator + # and manipulates the bus signals accordingly. + self.submodules.master = wishbone.Initiator(my_generator()) + # The "wishbone.Target" library component examines the bus signals + # and calls into our model object. + self.submodules.slave = wishbone.Target(MyModelWB()) + # The "wishbone.Tap" library component examines the bus at the slave port + # and displays the transactions on the console (/). + self.submodules.tap = wishbone.Tap(self.slave.bus) + # Connect the master to the slave. + self.submodules.intercon = wishbone.InterconnectPointToPoint(self.master.bus, self.slave.bus) + + def do_simulation(self, s): + # Terminate the simulation when the initiator is done (i.e. our generator is exhausted). + s.interrupt = self.master.done + +def main(): + tb = TB() + sim = Simulator(tb) + sim.run() + +main() + +# Output: +# +# Wrote in 0 cycle(s) +# +# Wrote in 0 cycle(s) +# +# Wrote in 0 cycle(s) +# +# Wrote in 1 cycle(s) +# +# Wrote in 1 cycle(s) +# +# Wrote in 2 cycle(s) +# ... +# +# Read 4 in 2 cycle(s) +# +# Read 5 in 2 cycle(s) +# +# Read 6 in 1 cycle(s) +# +# Read 7 in 1 cycle(s) +# ... -- 2.30.2