From 294c6f66373d29a9300a414fab24f1eefb473ccf Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 8 May 2018 14:02:38 +0200 Subject: [PATCH] re PR target/85480 (zero extension from xmm to zmm via _mm512_insert???x? not optimized) PR target/85480 * config/i386/sse.md (ssequaterinsnmode): New mode attribute. (*_vinsert_0): New pattern. * gcc.target/i386/avx512dq-pr85480-1.c: New test. * gcc.target/i386/avx512dq-pr85480-2.c: New test. From-SVN: r260039 --- gcc/ChangeLog | 6 +++ gcc/config/i386/sse.md | 37 ++++++++++++++++++ gcc/testsuite/ChangeLog | 6 +++ .../gcc.target/i386/avx512dq-pr85480-1.c | 26 +++++++++++++ .../gcc.target/i386/avx512dq-pr85480-2.c | 38 +++++++++++++++++++ 5 files changed, 113 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-pr85480-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-pr85480-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 924a033b8cd..74c90d83fbb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-05-08 Jakub Jelinek + + PR target/85480 + * config/i386/sse.md (ssequaterinsnmode): New mode attribute. + (*_vinsert_0): New pattern. + 2018-05-08 Richard Earnshaw PR target/85658 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 858c29ec3e2..aab4261343e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -581,6 +581,9 @@ (define_mode_attr ssequartermode [(V16SF "V4SF") (V8DF "V2DF") (V16SI "V4SI") (V8DI "V2DI")]) +(define_mode_attr ssequarterinsnmode + [(V16SF "V4SF") (V8DF "V2DF") (V16SI "TI") (V8DI "TI")]) + (define_mode_attr ssedoublemodelower [(V16QI "v16hi") (V32QI "v32hi") (V64QI "v64hi") (V8HI "v8si") (V16HI "v16si") (V32HI "v32si") @@ -12721,6 +12724,40 @@ DONE; }) +(define_insn "*_vinsert_0" + [(set (match_operand:AVX512_VEC 0 "register_operand" "=v,x,Yv") + (vec_merge:AVX512_VEC + (match_operand:AVX512_VEC 1 "reg_or_0_operand" "v,C,C") + (vec_duplicate:AVX512_VEC + (match_operand: 2 "nonimmediate_operand" "vm,xm,vm")) + (match_operand:SI 3 "const_int_operand" "n,n,n")))] + "TARGET_AVX512F + && (INTVAL (operands[3]) + == (GET_MODE_UNIT_SIZE (mode) == 4 ? 0xFFF0 : 0xFC))" +{ + if (which_alternative == 0) + return "vinsert\t{$0, %2, %1, %0|%0, %1, %2, 0}"; + switch (mode) + { + case E_V8DFmode: + return "vmovapd\t{%2, %x0|%x0, %2}"; + case E_V16SFmode: + return "vmovaps\t{%2, %x0|%x0, %2}"; + case E_V8DImode: + return which_alternative == 2 ? "vmovdqa64\t{%2, %x0|%x0, %2}" + : "vmovdqa\t{%2, %x0|%x0, %2}"; + case E_V16SImode: + return which_alternative == 2 ? "vmovdqa32\t{%2, %x0|%x0, %2}" + : "vmovdqa\t{%2, %x0|%x0, %2}"; + default: + gcc_unreachable (); + } +} + [(set_attr "type" "sselog,ssemov,ssemov") + (set_attr "length_immediate" "1,0,0") + (set_attr "prefix" "evex,vex,evex") + (set_attr "mode" ",,")]) + (define_insn "_vinsert_1" [(set (match_operand:AVX512_VEC 0 "register_operand" "=v") (vec_merge:AVX512_VEC diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2628d55dc23..6d92f7ee1c2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2018-05-08 Jakub Jelinek + + PR target/85480 + * gcc.target/i386/avx512dq-pr85480-1.c: New test. + * gcc.target/i386/avx512dq-pr85480-2.c: New test. + 2018-05-08 Richard Sandiford * g++.dg/other/sve_const_pred_1.C: Rename to... diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr85480-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr85480-1.c new file mode 100644 index 00000000000..681477f02c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr85480-1.c @@ -0,0 +1,26 @@ +/* PR target/85480 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512dq" } */ +/* { dg-final { scan-assembler-times "vmovaps\[^\n\r]*xmm0\[^\n\r]*xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovapd\[^\n\r]*xmm0\[^\n\r]*xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r]*xmm0\[^\n\r]*xmm0" 1 } } */ + +#include + +__m512 +f1 (__m128 a) +{ + return _mm512_insertf32x4 (_mm512_set1_ps (0.0f), a, 0); +} + +__m512d +f2 (__m128d a) +{ + return _mm512_insertf64x2 (_mm512_set1_pd (0.0), a, 0); +} + +__m512i +f3 (__m128i a) +{ + return _mm512_inserti32x4 (_mm512_set1_epi32 (0), a, 0); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr85480-2.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr85480-2.c new file mode 100644 index 00000000000..670870f4ede --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr85480-2.c @@ -0,0 +1,38 @@ +/* PR target/85480 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl" } */ +/* { dg-final { scan-assembler-times "vmovaps\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ +/* { dg-final { scan-assembler-times "vmovapd\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */ + +#include + +__m512 +f1 (__m128 a) +{ + register __m128 b __asm ("xmm16"); + asm ("" : "=v" (b) : "0" (a)); + register __m512 c __asm ("xmm17") = _mm512_insertf32x4 (_mm512_set1_ps (0.0f), b, 0); + asm ("" : "+v" (c)); + return c; +} + +__m512d +f2 (__m128d a) +{ + register __m128d b __asm ("xmm16"); + asm ("" : "=v" (b) : "0" (a)); + register __m512d c __asm ("xmm17") = _mm512_insertf64x2 (_mm512_set1_pd (0.0), b, 0); + asm ("" : "+v" (c)); + return c; +} + +__m512i +f3 (__m128i a) +{ + register __m128i b __asm ("xmm16"); + asm ("" : "=v" (b) : "0" (a)); + register __m512i c __asm ("xmm17") = _mm512_inserti32x4 (_mm512_set1_epi32 (0), b, 0); + asm ("" : "+v" (c)); + return c; +} -- 2.30.2