From 2955a65e5217b632a3e649a58ee4791a3befe02f Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 18:22:09 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 9eeb514ff..0d54ff69f 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -25,7 +25,7 @@ Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the Prefix instruction. More advanced features are similar to the Z80 `CPIR` instruction. If viewed one-dimensionally as an actual Vector ISA it introduces over 1.5 million 64-bit Vector instructions. SVP64, the instruction -format, is therefore best viewed as an orthogonal RISC-style "Prefixing" +format, is therefore best viewed as an orthogonal RISC-paradigm "Prefixing" subsystem instead. Except where explicitly stated all bit numbers remain as in the rest of -- 2.30.2