From 298c6dfc0f2380a16974b8d71f00759af2e38159 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 7 Sep 2020 16:59:40 +0100 Subject: [PATCH] bit of a big reorg of data structures ALU test_pipe_caller.py is now testing with a subset PowerDecoder2 and the field names need to change to match up. --- src/soc/decoder/decode2execute1.py | 1 + src/soc/decoder/isa/caller.py | 11 ++++++----- src/soc/decoder/power_decoder2.py | 13 +++++++------ src/soc/experiment/compalu_multi.py | 4 ++-- src/soc/experiment/compldst_multi.py | 8 ++++---- src/soc/experiment/test/test_compalu_multi.py | 12 ++++++------ src/soc/fu/alu/alu_input_record.py | 6 +++--- src/soc/fu/alu/output_stage.py | 2 +- src/soc/fu/alu/test/test_pipe_caller.py | 8 +++++--- src/soc/fu/branch/br_input_record.py | 2 +- src/soc/fu/common_output_stage.py | 2 +- src/soc/fu/ldst/ldst_input_record.py | 6 +++--- src/soc/fu/logical/logical_input_record.py | 6 +++--- src/soc/fu/mul/mul_input_record.py | 6 +++--- src/soc/fu/shift_rot/sr_input_record.py | 6 +++--- src/soc/fu/test/common.py | 4 ++-- 16 files changed, 51 insertions(+), 46 deletions(-) diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index 82815ade..f9aa722d 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -96,4 +96,5 @@ class Decode2ToExecute1Type(RecordObject): self.write_cr = Data(3, name="cr_out") # decode operand data + print ("decode2execute init", name, opkls) self.do = opkls(name) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 8862e22c..293c81c6 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -569,7 +569,7 @@ class ISACaller: # sigh reconstruct the assembly instruction name ov_en = yield self.dec2.e.do.oe.oe ov_ok = yield self.dec2.e.do.oe.ok - rc_en = yield self.dec2.e.do.rc.data + rc_en = yield self.dec2.e.do.rc.rc rc_ok = yield self.dec2.e.do.rc.ok # grrrr have to special-case MUL op (see DecodeOE) print("ov %d en %d rc %d en %d op %d" % \ @@ -582,9 +582,10 @@ class ISACaller: if not asmop.endswith("."): # don't add "." to "andis." if rc_en & rc_ok: asmop += "." - lk = yield self.dec2.e.do.lk - if lk: - asmop += "l" + if hasattr(self.dec2.e.do, "lk"): + lk = yield self.dec2.e.do.lk + if lk: + asmop += "l" print("int_op", int_op) if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]: AA = yield self.dec2.dec.fields.FormI.AA[0:-1] @@ -731,7 +732,7 @@ class ISACaller: if ov_en & ov_ok: yield from self.handle_overflow(inputs, results, overflow) - rc_en = yield self.dec2.e.do.rc.data + rc_en = yield self.dec2.e.do.rc.rc if rc_en: self.handle_comparison(results) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 2862804b..c2221707 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -598,11 +598,11 @@ class PowerDecodeSubset(Elaboratable): """ - def __init__(self, dec, fn_unit=None): + def __init__(self, dec, opkls=None, fn_name=None, col_subset=None): if dec is None: - self.opkls = fn_unit.opsubsetkls - self.fn_name = fn_unit.fnunit.name + self.opkls = opkls + self.fn_name = fn_name self.dec = create_pdecode(name=fn_name, col_subset=col_subset, row_subset=self.rowsubsetfn) else: @@ -614,7 +614,7 @@ class PowerDecodeSubset(Elaboratable): # state information needed by the Decoder (TODO: this as a Record) self.state = CoreState("dec2") - def rowsubsetfn(opcode, row): + def rowsubsetfn(self, opcode, row): return row['unit'] == self.fn_name def ports(self): @@ -768,7 +768,8 @@ class PowerDecode2(PowerDecodeSubset): comb += dec_c.sel_in.eq(op.in3_sel) comb += dec_o.sel_in.eq(op.out_sel) comb += dec_o2.sel_in.eq(op.out_sel) - comb += dec_o2.lk.eq(do.lk) + if hasattr(do, "lk"): + comb += dec_o2.lk.eq(do.lk) # registers a, b, c and out and out2 (LD/ST EA) comb += e.read_reg1.eq(dec_a.reg_out) @@ -807,7 +808,7 @@ class PowerDecode2(PowerDecodeSubset): with m.If(op.internal_op == MicrOp.OP_TRAP): # *DO NOT* call self.trap here. that would reset absolutely # rverything including destroying read of RA and RB. - comb += do.trapaddr.eq(0x70) # addr=0x700 (strip first nibble) + comb += self.do_copy("trapaddr", 0x70, True) # strip first nibble # check if instruction is privileged is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 79d4ccd1..d7e32f28 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -308,8 +308,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): if hasattr(op, "imm_data"): # select immediate if opcode says so. however also change the latch # to trigger *from* the opcode latch instead. - op_is_imm = op.imm_data.imm_ok - imm = op.imm_data.imm + op_is_imm = op.imm_data.ok + imm = op.imm_data.data self._mux_op(m, sl, op_is_imm, imm, 1) # create a latch/register for src1/src2 (even if it is a copy of imm) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 8aa252f8..9f64b4fa 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -405,9 +405,9 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0])) # select either immediate or src2 if opcode says so - op_is_imm = oper_r.imm_data.imm_ok + op_is_imm = oper_r.imm_data.ok src2_or_imm = Signal(self.data_wid, reset_less=True) - m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1])) + m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.data, srl[1])) # now do the ALU addr add: one cycle, and say "ready" (next cycle, too) comb += alu_o.eq(src1_or_z + src2_or_imm) # actual EA @@ -589,7 +589,7 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False, yield dut.src2_i.eq(src2) yield dut.src3_i.eq(src3) yield dut.oper_i.imm_data.imm.eq(imm) - yield dut.oper_i.imm_data.imm_ok.eq(imm_ok) + yield dut.oper_i.imm_data.ok.eq(imm_ok) yield dut.oper_i.update.eq(update) yield dut.issue_i.eq(1) yield @@ -645,7 +645,7 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False, yield dut.src2_i.eq(src2) yield dut.oper_i.zero_a.eq(zero_a) yield dut.oper_i.imm_data.imm.eq(imm) - yield dut.oper_i.imm_data.imm_ok.eq(imm_ok) + yield dut.oper_i.imm_data.ok.eq(imm_ok) yield dut.issue_i.eq(1) yield yield dut.issue_i.eq(0) diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index 97eb635f..3b4c562e 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -78,8 +78,8 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0): yield dut.src_i[1].eq(b) yield dut.oper_i.insn_type.eq(op) yield dut.oper_i.invert_in.eq(inv_a) - yield dut.oper_i.imm_data.imm.eq(imm) - yield dut.oper_i.imm_data.imm_ok.eq(imm_ok) + yield dut.oper_i.imm_data.data.eq(imm) + yield dut.oper_i.imm_data.ok.eq(imm_ok) yield dut.oper_i.zero_a.eq(zero_a) yield dut.issue_i.eq(1) yield @@ -286,8 +286,8 @@ class CompUnitParallelTest: # at the same time, present the operation yield self.dut.oper_i.insn_type.eq(self.op) yield self.dut.oper_i.invert_in.eq(self.inv_a) - yield self.dut.oper_i.imm_data.imm.eq(self.imm) - yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok) + yield self.dut.oper_i.imm_data.data.eq(self.imm) + yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok) yield self.dut.oper_i.zero_a.eq(self.zero_a) rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1) yield self.dut.rdmaskn.eq(rdmaskn) @@ -311,8 +311,8 @@ class CompUnitParallelTest: # TODO: deactivate rdmaskn when the busy_o cycle ends yield self.dut.oper_i.insn_type.eq(0) yield self.dut.oper_i.invert_in.eq(0) - yield self.dut.oper_i.imm_data.imm.eq(0) - yield self.dut.oper_i.imm_data.imm_ok.eq(0) + yield self.dut.oper_i.imm_data.data.eq(0) + yield self.dut.oper_i.imm_data.ok.eq(0) yield self.dut.oper_i.zero_a.eq(0) yield diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py index 07fdb5f7..fdafee52 100644 --- a/src/soc/fu/alu/alu_input_record.py +++ b/src/soc/fu/alu/alu_input_record.py @@ -13,9 +13,9 @@ class CompALUOpSubset(CompOpSubsetBase): def __init__(self, name=None): layout = (('insn_type', MicrOp), ('fn_unit', Function), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), - ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data - ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data + ('imm_data', Layout((("data", 64), ("ok", 1)))), + ('rc', Layout((("rc", 1), ("ok", 1)))), # Data + ('oe', Layout((("oe", 1), ("ok", 1)))), # Data ('invert_in', 1), ('zero_a', 1), ('invert_out', 1), diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index 44c90a37..2cf8c325 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -27,7 +27,7 @@ class ALUOutputStage(CommonOutputStage): # are actually required (oe enabled/set) otherwise the CompALU # can (will) ignore them. oe = Signal(reset_less=True) - comb += oe.eq(op.oe.oe & op.oe.oe_ok) + comb += oe.eq(op.oe.oe & op.oe.ok) with m.If(oe): # XXX see https://bugs.libre-soc.org/show_bug.cgi?id=319#c5 comb += xer_so_o.data.eq(xer_so_i[0] | xer_ov_i[0]) # SO diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 5cf37307..45701eb6 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -388,9 +388,11 @@ class TestRunner(unittest.TestCase): comb = m.d.comb instruction = Signal(32) - pdecode = create_pdecode() + fn_name = "ALU" + opkls = ALUPipeSpec.opsubsetkls - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) + pdecode = pdecode2.dec pspec = ALUPipeSpec(id_wid=2) m.submodules.alu = alu = ALUBasePipe(pspec) @@ -415,7 +417,7 @@ class TestRunner(unittest.TestCase): def check_alu_outputs(self, alu, dec2, sim, code): - rc = yield dec2.e.do.rc.data + rc = yield dec2.e.do.rc.rc cridx_ok = yield dec2.e.write_cr.ok cridx = yield dec2.e.write_cr.data diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py index 2e0a1e1e..41665488 100644 --- a/src/soc/fu/branch/br_input_record.py +++ b/src/soc/fu/branch/br_input_record.py @@ -16,7 +16,7 @@ class CompBROpSubset(CompOpSubsetBase): ('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), + ('imm_data', Layout((("data", 64), ("ok", 1)))), ('lk', 1), ('is_32bit', 1), ) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 401660c0..5a8b2f78 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -26,7 +26,7 @@ class CommonOutputStage(PipeModBase): xer_so_o = self.o.xer_so.data[0] so = Signal(reset_less=True) oe = Signal(reset_less=True) - comb += oe.eq(op.oe.oe & op.oe.oe_ok) + comb += oe.eq(op.oe.oe & op.oe.ok) with m.If(oe): comb += so.eq(xer_so_o) with m.Else(): diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py index f5b44d06..5560ba6c 100644 --- a/src/soc/fu/ldst/ldst_input_record.py +++ b/src/soc/fu/ldst/ldst_input_record.py @@ -15,10 +15,10 @@ class CompLDSTOpSubset(CompOpSubsetBase): """ def __init__(self, name=None): layout = (('insn_type', MicrOp), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), + ('imm_data', Layout((("data", 64), ("ok", 1)))), ('zero_a', 1), - ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # for later - ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # for later + ('rc', Layout((("rc", 1), ("ok", 1)))), # for later + ('oe', Layout((("oe", 1), ("ok", 1)))), # for later ('is_32bit', 1), ('is_signed', 1), ('data_len', 4), diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py index ad30488a..811823df 100644 --- a/src/soc/fu/logical/logical_input_record.py +++ b/src/soc/fu/logical/logical_input_record.py @@ -13,9 +13,9 @@ class CompLogicalOpSubset(CompOpSubsetBase): def __init__(self, name=None): layout = (('insn_type', MicrOp), ('fn_unit', Function), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), - ('rc', Layout((("rc", 1), ("rc_ok", 1)))), - ('oe', Layout((("oe", 1), ("oe_ok", 1)))), + ('imm_data', Layout((("data", 64), ("ok", 1)))), + ('rc', Layout((("rc", 1), ("ok", 1)))), + ('oe', Layout((("oe", 1), ("ok", 1)))), ('invert_in', 1), ('zero_a', 1), ('input_carry', CryIn), diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py index 1e667c05..1f321cbd 100644 --- a/src/soc/fu/mul/mul_input_record.py +++ b/src/soc/fu/mul/mul_input_record.py @@ -14,9 +14,9 @@ class CompMULOpSubset(CompOpSubsetBase): def __init__(self, name=None): layout = (('insn_type', MicrOp), ('fn_unit', Function), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), - ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data - ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data + ('imm_data', Layout((("data", 64), ("ok", 1)))), + ('rc', Layout((("rc", 1), ("ok", 1)))), # Data + ('oe', Layout((("oe", 1), ("ok", 1)))), # Data ('write_cr0', 1), ('is_32bit', 1), ('is_signed', 1), diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py index 67b351f6..49b7f52f 100644 --- a/src/soc/fu/shift_rot/sr_input_record.py +++ b/src/soc/fu/shift_rot/sr_input_record.py @@ -14,9 +14,9 @@ class CompSROpSubset(CompOpSubsetBase): def __init__(self, name=None): layout = (('insn_type', MicrOp), ('fn_unit', Function), - ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), - ('rc', Layout((("rc", 1), ("rc_ok", 1)))), - ('oe', Layout((("oe", 1), ("oe_ok", 1)))), + ('imm_data', Layout((("data", 64), ("ok", 1)))), + ('rc', Layout((("rc", 1), ("ok", 1)))), + ('oe', Layout((("oe", 1), ("ok", 1)))), ('write_cr0', 1), ('input_carry', CryIn), ('output_carry', 1), diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index c5917958..6e1e59a9 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -233,9 +233,9 @@ class ALUHelpers: if 'rb' in inp: yield alu.p.data_i.rb.eq(inp['rb']) # If there's an immediate, set the B operand to that - imm_ok = yield dec2.e.do.imm_data.imm_ok + imm_ok = yield dec2.e.do.imm_data.ok if imm_ok: - data2 = yield dec2.e.do.imm_data.imm + data2 = yield dec2.e.do.imm_data.data yield alu.p.data_i.rb.eq(data2) def set_int_rc(alu, dec2, inp): -- 2.30.2