From 29a09e1d380375bd3483d52ac5efdc8b47cc9851 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 27 Mar 2018 21:19:15 -0400 Subject: [PATCH] radeonsi: don't flush HTILE if there is no HTILE clear MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Samuel Pitoiset Tested-by: Dieter Nützel --- src/gallium/drivers/radeonsi/si_clear.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index f8136d2b2c4..4e05d9bf5b2 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -593,9 +593,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers, * * This hack decreases back-to-back ClearDepth performance. */ - if (sctx->screen->clear_db_cache_before_clear) { + if ((sctx->db_depth_clear || sctx->db_stencil_clear) && + sctx->screen->clear_db_cache_before_clear) sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB; - } } si_blitter_begin(sctx, SI_CLEAR); -- 2.30.2