From 29ae291964cb24cf8e2495e85195a16d5f3e6a7f Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Mon, 24 Oct 2022 21:20:39 +0300 Subject: [PATCH] bitmanip.mdwn: support shadd/shadduw instructions --- openpower/isa/bitmanip.mdwn | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn index d5b9dddb..0863a5cb 100644 --- a/openpower/isa/bitmanip.mdwn +++ b/openpower/isa/bitmanip.mdwn @@ -99,3 +99,52 @@ Pseudo-code: Special Registers Altered: CR0 (if Rc=1) + +# Add With Shift By Immediate + +Z23-Form + +* shadd RT,RA,RB,sm (Rc=0) +* shadd. RT,RA,RB,sm (Rc=1) + +Pseudo-code: + + switch (sm) + case (0): + sum[0:XLEN-1] <- (((RB)[0:XLEN-1-1] || [0]*1) + (RA)) + case (1): + sum[0:XLEN-1] <- (((RB)[0:XLEN-2-1] || [0]*2) + (RA)) + case (2): + sum[0:XLEN-1] <- (((RB)[0:XLEN-3-1] || [0]*3) + (RA)) + default: + sum[0:XLEN-1] <- (((RB)[0:XLEN-4-1] || [0]*4) + (RA)) + RT <- sum + +Special Registers Altered: + + CR0 (if Rc=1) + +# Add With Shift By Immediate Unsinged Word + +Z23-Form + +* shadduw RT,RA,RB,sm (Rc=0) +* shadduw. RT,RA,RB,sm (Rc=1) + +Pseudo-code: + + n <- (([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]) + switch (sm) + case (0): + sum[0:XLEN-1] = ((n[0:XLEN-1-1] || [0]*1) + (RA)) + case (1): + sum[0:XLEN-1] = ((n[0:XLEN-2-1] || [0]*2) + (RA)) + case (2): + sum[0:XLEN-1] = ((n[0:XLEN-3-1] || [0]*3) + (RA)) + default: + sum[0:XLEN-1] = ((n[0:XLEN-4-1] || [0]*4) + (RA)) + RT <- sum + +Special Registers Altered: + + CR0 (if Rc=1) -- 2.30.2