From 29ae93642d81acf4bba804d2929de1527d319b13 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Wed, 26 Mar 2003 16:04:08 +0000 Subject: [PATCH] power4.md: Allow delay between dispatch and function units for simple instructions. * config/rs6000/power4.md: Allow delay between dispatch and function units for simple instructions. Correct store units. Allow branch to occupy as many dispatch slots as necessary. From-SVN: r64896 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/power4.md | 43 +++++++++++++++++++++++-------------- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06993a1fddc..3726073ab26 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2003-03-26 David Edelsohn + + * config/rs6000/power4.md: Allow delay between dispatch and + function units for simple instructions. Correct store units. + Allow branch to occupy as many dispatch slots as necessary. + 2003-03-26 Jakub Jelinek * config/ia64/ia64.c (ia64_expand_op_and_fetch): Fix comment. diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index bf0a92bfe12..35f1ba216fe 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -37,9 +37,12 @@ (define_reservation "q1_power4" "du1_power4|du4_power4") (define_reservation "q2_power4" "du2_power4|du3_power4") +(define_reservation "q4_power4" "du1_power4|du2_power4|du3_power4|du4_power4") -(define_reservation "lsq_power4" "((du1_power4|du4_power4),lsu1_power4)\ - |((du2_power4|du3_power4),lsu2_power4)") +(define_reservation "lsq_power4" "(q1_power4,lsu1_power4)\ + |(q2_power4,lsu2_power4)\ + |(du3_power4,nothing,lsu2_power4)\ + |(du4_power4,nothing,lsu1_power4)") (define_reservation "lsuq_power4" "((du1_power4+du2_power4),lsu1_power4+iu2_power4)\ @@ -51,17 +54,21 @@ "(du1_power4+du2_power4+du3_power4+du4_power4),\ iu1_power4,(lsu2_power4+iu2_power4)") -(define_reservation "iq_power4" "((du1_power4|du4_power4),iu1_power4)\ - |((du2_power4|du3_power4),iu2_power4)") +(define_reservation "iq_power4" "(q1_power4,iu1_power4)\ + |(q2_power4,iu2_power4)\ + |(du3_power4,nothing,iu2_power4)\ + |(du4_power4,nothing,iu1_power4)") -(define_reservation "fpq_power4" "((du1_power4|du4_power4),fpu1_power4)\ - |((du2_power4|du3_power4),fpu2_power4)") +(define_reservation "fpq_power4" "(q1_power4,fpu1_power4)\ + |(q2_power4,fpu2_power4)\ + |(du3_power4,nothing,fpu2_power4)\ + |(du4_power4,nothing,fpu1_power4)") (define_reservation "vq_power4" - "(du1_power4|du2_power4|du3_power4|du4_power4),vec_power4") + "(q4_power4,vec_power4)|(q4_power4,nothing,vec_power4)") (define_reservation "vpq_power4" - "(du1_power4|du2_power4|du3_power4|du4_power4),\ - vecperm_power4") + "(q4_power4,vecperm_power4)\ + |(q4_power4,nothing,vecperm_power4)") ; Dispatch slots are allocated in order conforming to program order. @@ -129,8 +136,8 @@ (define_insn_reservation "power4-store" 1 (and (eq_attr "type" "store") (eq_attr "cpu" "power4")) - "((du1_power4|du4_power4),lsu1_power4,iu2_power4)\ - |((du2_power4|du3_power4),lsu2_power4,iu1_power4)") + "(q1_power4,lsu1_power4,iu1_power4)\ + |(q2_power4,lsu2_power4,iu2_power4)") (define_insn_reservation "power4-store-update" 1 (and (eq_attr "type" "store_u") @@ -145,8 +152,8 @@ (define_insn_reservation "power4-fpstore" 1 (and (eq_attr "type" "fpstore") (eq_attr "cpu" "power4")) - "((du1_power4|du4_power4),lsu1_power4,fpu1_power4)\ - |((du2_power4|du3_power4),lsu2_power4,fpu2_power4)") + "(q1_power4,lsu1_power4,fpu1_power4)\ + |(q2_power4,lsu2_power4,fpu2_power4)") (define_insn_reservation "power4-fpstore-update" 1 (and (eq_attr "type" "fpstore_u") @@ -165,8 +172,8 @@ (define_insn_reservation "power4-vecstore" 1 (and (eq_attr "type" "vecstore") (eq_attr "cpu" "power4")) - "((du1_power4|du4_power4),lsu1_power4,vec_power4)\ - |((du2_power4|du3_power4),lsu2_power4,vec_power4)") + "(q1_power4,lsu1_power4,vec_power4)\ + |(q2_power4,lsu2_power4,vec_power4)") ; Integer latency is 2 cycles @@ -228,7 +235,11 @@ (define_insn_reservation "power4-branch" 2 (and (eq_attr "type" "jmpreg,branch") (eq_attr "cpu" "power4")) - "du5_power4,bpu_power4") + "(du5_power4\ + |du4_power4+du5_power4\ + |du3_power4+du4_power4+du5_power4\ + |du2_power4+du3_power4+du4_power4+du5_power4\ + |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4") ; Condition Register logical ops are split if non-destructive (RT != RB) -- 2.30.2