From 29b7163bf1dc2fe89b9530f038ae93eb2e4e6f9b Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Mon, 8 Jun 2020 01:28:51 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise
 that RA (src1) can be zero

---
 f5/68371d6beb25656ffdf0d4efaade4f7569a30b | 84 +++++++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 f5/68371d6beb25656ffdf0d4efaade4f7569a30b

diff --git a/f5/68371d6beb25656ffdf0d4efaade4f7569a30b b/f5/68371d6beb25656ffdf0d4efaade4f7569a30b
new file mode 100644
index 0000000..7e6b261
--- /dev/null
+++ b/f5/68371d6beb25656ffdf0d4efaade4f7569a30b
@@ -0,0 +1,84 @@
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+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Mon, 08 Jun 2020 01:28:51 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+Message-ID: <bug-336-13-v4MT4XzUah@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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-- 
2.30.2