From 29d89ec1e6c771b49f6f7e3bf225fcb46990f8ed Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Sun, 15 May 2011 22:33:25 -0700
Subject: [PATCH] [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts

---
 riscv/execute.h                           | 414 +++++++++++-----------
 riscv/insns/{fldseg_v.h => fmovn.h}       |   0
 riscv/insns/{fldsegst_v.h => fmovz.h}     |   0
 riscv/insns/{flwseg_v.h => movn.h}        |   0
 riscv/insns/{flwsegst_v.h => movz.h}      |   0
 riscv/insns/{fld_v.h => vfld.h}           |   0
 riscv/insns/{fsdseg_v.h => vflsegd.h}     |   0
 riscv/insns/{fsdsegst_v.h => vflsegstd.h} |   0
 riscv/insns/{fswseg_v.h => vflsegstw.h}   |   0
 riscv/insns/{fswsegst_v.h => vflsegw.h}   |   0
 riscv/insns/{fldst_v.h => vflstd.h}       |   0
 riscv/insns/{flwst_v.h => vflstw.h}       |   0
 riscv/insns/{flw_v.h => vflw.h}           |   0
 riscv/insns/{fmov_su.h => vfmst.h}        |   0
 riscv/insns/{fmov_sv.h => vfmsv.h}        |   0
 riscv/insns/{fmov_us.h => vfmts.h}        |   0
 riscv/insns/{fmov_vv.h => vfmvv.h}        |   0
 riscv/insns/{fsd_v.h => vfsd.h}           |   0
 riscv/insns/{lbseg_v.h => vfssegd.h}      |   0
 riscv/insns/{lbsegst_v.h => vfssegstd.h}  |   0
 riscv/insns/{lbuseg_v.h => vfssegstw.h}   |   0
 riscv/insns/{lbusegst_v.h => vfssegw.h}   |   0
 riscv/insns/{fsdst_v.h => vfsstd.h}       |   0
 riscv/insns/{fswst_v.h => vfsstw.h}       |   0
 riscv/insns/{fsw_v.h => vfsw.h}           |   0
 riscv/insns/{lb_v.h => vlb.h}             |   0
 riscv/insns/{lbu_v.h => vlbu.h}           |   0
 riscv/insns/{ld_v.h => vld.h}             |   0
 riscv/insns/{lh_v.h => vlh.h}             |   0
 riscv/insns/{lhu_v.h => vlhu.h}           |   0
 riscv/insns/{ldseg_v.h => vlsegb.h}       |   0
 riscv/insns/{ldsegst_v.h => vlsegbu.h}    |   0
 riscv/insns/{lhseg_v.h => vlsegd.h}       |   0
 riscv/insns/{lhsegst_v.h => vlsegh.h}     |   0
 riscv/insns/{lhuseg_v.h => vlseghu.h}     |   0
 riscv/insns/{lhusegst_v.h => vlsegstb.h}  |   0
 riscv/insns/{lwseg_v.h => vlsegstbu.h}    |   0
 riscv/insns/{lwsegst_v.h => vlsegstd.h}   |   0
 riscv/insns/{lwuseg_v.h => vlsegsth.h}    |   0
 riscv/insns/{lwusegst_v.h => vlsegsthu.h} |   0
 riscv/insns/{sbseg_v.h => vlsegstw.h}     |   0
 riscv/insns/{sbsegst_v.h => vlsegstwu.h}  |   0
 riscv/insns/{sdseg_v.h => vlsegw.h}       |   0
 riscv/insns/{sdsegst_v.h => vlsegwu.h}    |   0
 riscv/insns/{lbst_v.h => vlstb.h}         |   0
 riscv/insns/{lbust_v.h => vlstbu.h}       |   0
 riscv/insns/{ldst_v.h => vlstd.h}         |   0
 riscv/insns/{lhst_v.h => vlsth.h}         |   0
 riscv/insns/{lhust_v.h => vlsthu.h}       |   0
 riscv/insns/{lwst_v.h => vlstw.h}         |   0
 riscv/insns/{lwust_v.h => vlstwu.h}       |   0
 riscv/insns/{lw_v.h => vlw.h}             |   0
 riscv/insns/{lwu_v.h => vlwu.h}           |   0
 riscv/insns/{mov_su.h => vmst.h}          |   0
 riscv/insns/{mov_sv.h => vmsv.h}          |   0
 riscv/insns/{mov_us.h => vmts.h}          |   0
 riscv/insns/{mov_vv.h => vmvv.h}          |   0
 riscv/insns/{sb_v.h => vsb.h}             |   0
 riscv/insns/{sd_v.h => vsd.h}             |   0
 riscv/insns/{setvl.h => vsetvl.h}         |   0
 riscv/insns/{sh_v.h => vsh.h}             |   0
 riscv/insns/{shseg_v.h => vssegb.h}       |   0
 riscv/insns/{shsegst_v.h => vssegd.h}     |   0
 riscv/insns/{swseg_v.h => vssegh.h}       |   0
 riscv/insns/{swsegst_v.h => vssegstb.h}   |   0
 riscv/insns/vssegstd.h                    |   0
 riscv/insns/vssegsth.h                    |   0
 riscv/insns/vssegstw.h                    |   0
 riscv/insns/vssegw.h                      |   0
 riscv/insns/{sbst_v.h => vsstb.h}         |   0
 riscv/insns/{sdst_v.h => vsstd.h}         |   0
 riscv/insns/{shst_v.h => vssth.h}         |   0
 riscv/insns/{swst_v.h => vsstw.h}         |   0
 riscv/insns/{sw_v.h => vsw.h}             |   0
 riscv/insns/vtcfgivl.h                    |   0
 riscv/insns/{vcfgivl.h => vvcfgivl.h}     |   0
 76 files changed, 212 insertions(+), 202 deletions(-)
 rename riscv/insns/{fldseg_v.h => fmovn.h} (100%)
 rename riscv/insns/{fldsegst_v.h => fmovz.h} (100%)
 rename riscv/insns/{flwseg_v.h => movn.h} (100%)
 rename riscv/insns/{flwsegst_v.h => movz.h} (100%)
 rename riscv/insns/{fld_v.h => vfld.h} (100%)
 rename riscv/insns/{fsdseg_v.h => vflsegd.h} (100%)
 rename riscv/insns/{fsdsegst_v.h => vflsegstd.h} (100%)
 rename riscv/insns/{fswseg_v.h => vflsegstw.h} (100%)
 rename riscv/insns/{fswsegst_v.h => vflsegw.h} (100%)
 rename riscv/insns/{fldst_v.h => vflstd.h} (100%)
 rename riscv/insns/{flwst_v.h => vflstw.h} (100%)
 rename riscv/insns/{flw_v.h => vflw.h} (100%)
 rename riscv/insns/{fmov_su.h => vfmst.h} (100%)
 rename riscv/insns/{fmov_sv.h => vfmsv.h} (100%)
 rename riscv/insns/{fmov_us.h => vfmts.h} (100%)
 rename riscv/insns/{fmov_vv.h => vfmvv.h} (100%)
 rename riscv/insns/{fsd_v.h => vfsd.h} (100%)
 rename riscv/insns/{lbseg_v.h => vfssegd.h} (100%)
 rename riscv/insns/{lbsegst_v.h => vfssegstd.h} (100%)
 rename riscv/insns/{lbuseg_v.h => vfssegstw.h} (100%)
 rename riscv/insns/{lbusegst_v.h => vfssegw.h} (100%)
 rename riscv/insns/{fsdst_v.h => vfsstd.h} (100%)
 rename riscv/insns/{fswst_v.h => vfsstw.h} (100%)
 rename riscv/insns/{fsw_v.h => vfsw.h} (100%)
 rename riscv/insns/{lb_v.h => vlb.h} (100%)
 rename riscv/insns/{lbu_v.h => vlbu.h} (100%)
 rename riscv/insns/{ld_v.h => vld.h} (100%)
 rename riscv/insns/{lh_v.h => vlh.h} (100%)
 rename riscv/insns/{lhu_v.h => vlhu.h} (100%)
 rename riscv/insns/{ldseg_v.h => vlsegb.h} (100%)
 rename riscv/insns/{ldsegst_v.h => vlsegbu.h} (100%)
 rename riscv/insns/{lhseg_v.h => vlsegd.h} (100%)
 rename riscv/insns/{lhsegst_v.h => vlsegh.h} (100%)
 rename riscv/insns/{lhuseg_v.h => vlseghu.h} (100%)
 rename riscv/insns/{lhusegst_v.h => vlsegstb.h} (100%)
 rename riscv/insns/{lwseg_v.h => vlsegstbu.h} (100%)
 rename riscv/insns/{lwsegst_v.h => vlsegstd.h} (100%)
 rename riscv/insns/{lwuseg_v.h => vlsegsth.h} (100%)
 rename riscv/insns/{lwusegst_v.h => vlsegsthu.h} (100%)
 rename riscv/insns/{sbseg_v.h => vlsegstw.h} (100%)
 rename riscv/insns/{sbsegst_v.h => vlsegstwu.h} (100%)
 rename riscv/insns/{sdseg_v.h => vlsegw.h} (100%)
 rename riscv/insns/{sdsegst_v.h => vlsegwu.h} (100%)
 rename riscv/insns/{lbst_v.h => vlstb.h} (100%)
 rename riscv/insns/{lbust_v.h => vlstbu.h} (100%)
 rename riscv/insns/{ldst_v.h => vlstd.h} (100%)
 rename riscv/insns/{lhst_v.h => vlsth.h} (100%)
 rename riscv/insns/{lhust_v.h => vlsthu.h} (100%)
 rename riscv/insns/{lwst_v.h => vlstw.h} (100%)
 rename riscv/insns/{lwust_v.h => vlstwu.h} (100%)
 rename riscv/insns/{lw_v.h => vlw.h} (100%)
 rename riscv/insns/{lwu_v.h => vlwu.h} (100%)
 rename riscv/insns/{mov_su.h => vmst.h} (100%)
 rename riscv/insns/{mov_sv.h => vmsv.h} (100%)
 rename riscv/insns/{mov_us.h => vmts.h} (100%)
 rename riscv/insns/{mov_vv.h => vmvv.h} (100%)
 rename riscv/insns/{sb_v.h => vsb.h} (100%)
 rename riscv/insns/{sd_v.h => vsd.h} (100%)
 rename riscv/insns/{setvl.h => vsetvl.h} (100%)
 rename riscv/insns/{sh_v.h => vsh.h} (100%)
 rename riscv/insns/{shseg_v.h => vssegb.h} (100%)
 rename riscv/insns/{shsegst_v.h => vssegd.h} (100%)
 rename riscv/insns/{swseg_v.h => vssegh.h} (100%)
 rename riscv/insns/{swsegst_v.h => vssegstb.h} (100%)
 create mode 100644 riscv/insns/vssegstd.h
 create mode 100644 riscv/insns/vssegsth.h
 create mode 100644 riscv/insns/vssegstw.h
 create mode 100644 riscv/insns/vssegw.h
 rename riscv/insns/{sbst_v.h => vsstb.h} (100%)
 rename riscv/insns/{sdst_v.h => vsstd.h} (100%)
 rename riscv/insns/{shst_v.h => vssth.h} (100%)
 rename riscv/insns/{swst_v.h => vsstw.h} (100%)
 rename riscv/insns/{sw_v.h => vsw.h} (100%)
 create mode 100644 riscv/insns/vtcfgivl.h
 rename riscv/insns/{vcfgivl.h => vvcfgivl.h} (100%)

diff --git a/riscv/execute.h b/riscv/execute.h
index b258957..6ea79c8 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -113,359 +113,319 @@ switch((insn.bits >> 0x0) & 0x7f)
   }
   case 0xb:
   {
-        if((insn.bits & 0x1ffff) == 0x230b)
+        if((insn.bits & 0x1ffff) == 0x128b)
         {
-          #include "insns/lwuseg_v.h"
+          #include "insns/vlsthu.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x10b)
+        if((insn.bits & 0xfff) == 0xb0b)
         {
-          #include "insns/lw_v.h"
+          #include "insns/vlsegstwu.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x30b)
         {
-          #include "insns/lwu_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x1810b)
-        {
-          #include "insns/fmov_su.h"
+          #include "insns/vlwu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x290b)
-        {
-          #include "insns/swseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x280b)
+        if((insn.bits & 0x3fffff) == 0x8b)
         {
-          #include "insns/sbseg_v.h"
+          #include "insns/vlh.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x20b)
+        if((insn.bits & 0x1ffff) == 0x158b)
         {
-          #include "insns/lbu_v.h"
+          #include "insns/vflstd.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x100b)
+        if((insn.bits & 0x3fffff) == 0xb)
         {
-          #include "insns/lbst_v.h"
+          #include "insns/vlb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x218b)
+        if((insn.bits & 0x3fffff) == 0x18b)
         {
-          #include "insns/ldseg_v.h"
+          #include "insns/vld.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x180b)
+        if((insn.bits & 0x1ffff) == 0x150b)
         {
-          #include "insns/sbst_v.h"
+          #include "insns/vflstw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x58b)
+        if((insn.bits & 0x3fffff) == 0x10b)
         {
-          #include "insns/fld_v.h"
+          #include "insns/vlw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x208b)
+        if((insn.bits & 0x1ffff) == 0x120b)
         {
-          #include "insns/lhseg_v.h"
+          #include "insns/vlstbu.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x220b)
         {
-          #include "insns/lbuseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x108b)
-        {
-          #include "insns/lhst_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x128b)
-        {
-          #include "insns/lhust_v.h"
+          #include "insns/vlsegbu.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1008b)
+        if((insn.bits & 0xfff) == 0xa8b)
         {
-          #include "insns/mov_sv.h"
+          #include "insns/vlsegsthu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1010b)
+        if((insn.bits & 0x1ffff) == 0x110b)
         {
-          #include "insns/mov_su.h"
+          #include "insns/vlstw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x18b)
+        if((insn.bits & 0x1ffff) == 0x108b)
         {
-          #include "insns/ld_v.h"
+          #include "insns/vlsth.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1d0b)
+        if((insn.bits & 0x1ffff) == 0x100b)
         {
-          #include "insns/fswst_v.h"
+          #include "insns/vlstb.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xd8b)
+        if((insn.bits & 0x1ffff) == 0x118b)
         {
-          #include "insns/fsd_v.h"
+          #include "insns/vlstd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1808b)
+        if((insn.bits & 0xfff) == 0xa0b)
         {
-          #include "insns/fmov_sv.h"
+          #include "insns/vlsegstbu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x2d8b)
+        if((insn.bits & 0x3fffff) == 0x28b)
         {
-          #include "insns/fsdseg_v.h"
+          #include "insns/vlhu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x190b)
+        if((insn.bits & 0xfff) == 0x90b)
         {
-          #include "insns/swst_v.h"
+          #include "insns/vlsegstw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1d8b)
+        if((insn.bits & 0x1ffff) == 0x130b)
         {
-          #include "insns/fsdst_v.h"
+          #include "insns/vlstwu.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xb)
+        if((insn.bits & 0xfff) == 0x80b)
         {
-          #include "insns/lb_v.h"
+          #include "insns/vlsegstb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x118b)
+        if((insn.bits & 0xfff) == 0x98b)
         {
-          #include "insns/ldst_v.h"
+          #include "insns/vlsegstd.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x258b)
         {
-          #include "insns/fldseg_v.h"
+          #include "insns/vflsegd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x8b)
-        {
-          #include "insns/lh_v.h"
-          break;
-        }
-        if((insn.bits & 0x3fffff) == 0x28b)
+        if((insn.bits & 0x1ffff) == 0x250b)
         {
-          #include "insns/lhu_v.h"
+          #include "insns/vflsegw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1018b)
+        if((insn.bits & 0xfff) == 0x88b)
         {
-          #include "insns/mov_us.h"
+          #include "insns/vlsegsth.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xd0b)
+        if((insn.bits & 0xfff) == 0xd0b)
         {
-          #include "insns/fsw_v.h"
+          #include "insns/vflsegstw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x158b)
+        if((insn.bits & 0xfff) == 0xd8b)
         {
-          #include "insns/fldst_v.h"
+          #include "insns/vflsegstd.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x250b)
+        if((insn.bits & 0x3fffff) == 0x58b)
         {
-          #include "insns/flwseg_v.h"
+          #include "insns/vfld.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x200b)
+        if((insn.bits & 0x1ffff) == 0x230b)
         {
-          #include "insns/lbseg_v.h"
+          #include "insns/vlsegwu.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x50b)
         {
-          #include "insns/flw_v.h"
-          break;
-        }
-        if((insn.bits & 0x3fffff) == 0x90b)
-        {
-          #include "insns/sw_v.h"
+          #include "insns/vflw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x298b)
-        {
-          #include "insns/sdseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x130b)
+        if((insn.bits & 0x1ffff) == 0x200b)
         {
-          #include "insns/lwust_v.h"
+          #include "insns/vlsegb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x150b)
+        if((insn.bits & 0x1ffff) == 0x218b)
         {
-          #include "insns/flwst_v.h"
+          #include "insns/vlsegd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x88b)
+        if((insn.bits & 0x1ffff) == 0x208b)
         {
-          #include "insns/sh_v.h"
+          #include "insns/vlsegh.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x210b)
         {
-          #include "insns/lwseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x2d0b)
-        {
-          #include "insns/fswseg_v.h"
+          #include "insns/vlsegw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x288b)
+        if((insn.bits & 0x3fffff) == 0x20b)
         {
-          #include "insns/shseg_v.h"
+          #include "insns/vlbu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1818b)
+        if((insn.bits & 0x1ffff) == 0x228b)
         {
-          #include "insns/fmov_us.h"
+          #include "insns/vlseghu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x228b)
+        throw trap_illegal_instruction;
+    break;
+  }
+  case 0xc:
+  {
+    #include "insns/c_sd.h"
+    break;
+  }
+  case 0xd:
+  {
+    #include "insns/c_sw.h"
+    break;
+  }
+  case 0xf:
+  {
+        if((insn.bits & 0x1ffff) == 0x150f)
         {
-          #include "insns/lhuseg_v.h"
+          #include "insns/vfsstw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x120b)
+        if((insn.bits & 0xfff) == 0x90f)
         {
-          #include "insns/lbust_v.h"
+          #include "insns/vssegstw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x98b)
+        if((insn.bits & 0xfff) == 0x98f)
         {
-          #include "insns/sd_v.h"
+          #include "insns/vssegstd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1000b)
+        if((insn.bits & 0xfff) == 0x80f)
         {
-          #include "insns/mov_vv.h"
+          #include "insns/vssegstb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x110b)
+        if((insn.bits & 0xfff) == 0x88f)
         {
-          #include "insns/lwst_v.h"
+          #include "insns/vssegsth.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x198b)
+        if((insn.bits & 0x3fffff) == 0x10f)
         {
-          #include "insns/sdst_v.h"
+          #include "insns/vsw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1800b)
+        if((insn.bits & 0xfff) == 0xd8f)
         {
-          #include "insns/fmov_vv.h"
+          #include "insns/vfssegstd.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x188b)
+        if((insn.bits & 0x3fffff) == 0xf)
         {
-          #include "insns/shst_v.h"
+          #include "insns/vsb.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x80b)
+        if((insn.bits & 0x1ffff) == 0x110f)
         {
-          #include "insns/sb_v.h"
+          #include "insns/vsstw.h"
           break;
         }
-        throw trap_illegal_instruction;
-    break;
-  }
-  case 0xc:
-  {
-    #include "insns/c_sd.h"
-    break;
-  }
-  case 0xd:
-  {
-    #include "insns/c_sw.h"
-    break;
-  }
-  case 0xf:
-  {
-        if((insn.bits & 0xfff) == 0x20f)
+        if((insn.bits & 0x1ffff) == 0x108f)
         {
-          #include "insns/lbusegst_v.h"
+          #include "insns/vssth.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x18f)
+        if((insn.bits & 0x1ffff) == 0x100f)
         {
-          #include "insns/ldsegst_v.h"
+          #include "insns/vsstb.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x98f)
+        if((insn.bits & 0x1ffff) == 0x118f)
         {
-          #include "insns/sdsegst_v.h"
+          #include "insns/vsstd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x30f)
+        if((insn.bits & 0x1ffff) == 0x218f)
         {
-          #include "insns/lwusegst_v.h"
+          #include "insns/vssegd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x80f)
+        if((insn.bits & 0x1ffff) == 0x158f)
         {
-          #include "insns/sbsegst_v.h"
+          #include "insns/vfsstd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x58f)
+        if((insn.bits & 0xfff) == 0xd0f)
         {
-          #include "insns/fldsegst_v.h"
+          #include "insns/vfssegstw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x28f)
+        if((insn.bits & 0x1ffff) == 0x210f)
         {
-          #include "insns/lhusegst_v.h"
+          #include "insns/vssegw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0xf)
+        if((insn.bits & 0x3fffff) == 0x18f)
         {
-          #include "insns/lbsegst_v.h"
+          #include "insns/vsd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0xd8f)
+        if((insn.bits & 0x3fffff) == 0x8f)
         {
-          #include "insns/fsdsegst_v.h"
+          #include "insns/vsh.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0xd0f)
+        if((insn.bits & 0x1ffff) == 0x208f)
         {
-          #include "insns/fswsegst_v.h"
+          #include "insns/vssegh.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x88f)
+        if((insn.bits & 0x3fffff) == 0x50f)
         {
-          #include "insns/shsegst_v.h"
+          #include "insns/vfsw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x50f)
+        if((insn.bits & 0x3fffff) == 0x58f)
         {
-          #include "insns/flwsegst_v.h"
+          #include "insns/vfsd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x10f)
+        if((insn.bits & 0x1ffff) == 0x250f)
         {
-          #include "insns/lwsegst_v.h"
+          #include "insns/vfssegw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x90f)
+        if((insn.bits & 0x1ffff) == 0x200f)
         {
-          #include "insns/swsegst_v.h"
+          #include "insns/vssegb.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x8f)
+        if((insn.bits & 0x1ffff) == 0x258f)
         {
-          #include "insns/lhsegst_v.h"
+          #include "insns/vfssegd.h"
           break;
         }
         throw trap_illegal_instruction;
@@ -583,14 +543,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
@@ -1063,14 +1023,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
@@ -1493,11 +1453,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fsgnjn_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xa053)
-        {
-          #include "insns/fcvt_w_s.h"
-          break;
-        }
         if((insn.bits & 0x3ff1ff) == 0xd0d3)
         {
           #include "insns/fcvt_d_lu.h"
@@ -1563,6 +1518,11 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fsub_d.h"
           break;
         }
+        if((insn.bits & 0x3ff1ff) == 0xa053)
+        {
+          #include "insns/fcvt_w_s.h"
+          break;
+        }
         if((insn.bits & 0x3ff1ff) == 0x4053)
         {
           #include "insns/fsqrt_s.h"
@@ -1628,14 +1588,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
@@ -1858,19 +1818,64 @@ switch((insn.bits >> 0x0) & 0x7f)
   }
   case 0x73:
   {
-        if((insn.bits & 0x3ff) == 0x73)
+        if((insn.bits & 0x3ff) == 0xf3)
+        {
+          #include "insns/vvcfgivl.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x2f3)
         {
-          #include "insns/vcfgivl.h"
+          #include "insns/vsetvl.h"
           break;
         }
-        if((insn.bits & 0xf80003ff) == 0x173)
+        if((insn.bits & 0x1ffff) == 0x1173)
+        {
+          #include "insns/vfmst.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1973)
+        {
+          #include "insns/vfmts.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x973)
+        {
+          #include "insns/vfmsv.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1873)
+        {
+          #include "insns/vmts.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x73)
+        {
+          #include "insns/vmvv.h"
+          break;
+        }
+        if((insn.bits & 0x3ff) == 0x1f3)
+        {
+          #include "insns/vtcfgivl.h"
+          break;
+        }
+        if((insn.bits & 0xf80003ff) == 0x3f3)
         {
           #include "insns/vf.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xf3)
+        if((insn.bits & 0x3fffff) == 0x173)
+        {
+          #include "insns/vfmvv.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x873)
+        {
+          #include "insns/vmsv.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1073)
         {
-          #include "insns/setvl.h"
+          #include "insns/vmst.h"
           break;
         }
         throw trap_illegal_instruction;
@@ -1893,9 +1898,14 @@ switch((insn.bits >> 0x0) & 0x7f)
   }
   case 0x77:
   {
-        if((insn.bits & 0x7ffffff) == 0x277)
+        if((insn.bits & 0x1ffff) == 0x2f7)
         {
-          #include "insns/rdcycle.h"
+          #include "insns/movn.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x277)
+        {
+          #include "insns/movz.h"
           break;
         }
         if((insn.bits & 0xffffffff) == 0x177)
@@ -1913,14 +1923,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/utidx.h"
           break;
         }
-        if((insn.bits & 0x7ffffff) == 0xa77)
+        if((insn.bits & 0x1ffff) == 0x3f7)
         {
-          #include "insns/rdinstret.h"
+          #include "insns/fmovn.h"
           break;
         }
-        if((insn.bits & 0x7ffffff) == 0x677)
+        if((insn.bits & 0x1ffff) == 0x377)
         {
-          #include "insns/rdtime.h"
+          #include "insns/fmovz.h"
           break;
         }
         if((insn.bits & 0xffffffff) == 0x77)
@@ -1953,14 +1963,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
diff --git a/riscv/insns/fldseg_v.h b/riscv/insns/fmovn.h
similarity index 100%
rename from riscv/insns/fldseg_v.h
rename to riscv/insns/fmovn.h
diff --git a/riscv/insns/fldsegst_v.h b/riscv/insns/fmovz.h
similarity index 100%
rename from riscv/insns/fldsegst_v.h
rename to riscv/insns/fmovz.h
diff --git a/riscv/insns/flwseg_v.h b/riscv/insns/movn.h
similarity index 100%
rename from riscv/insns/flwseg_v.h
rename to riscv/insns/movn.h
diff --git a/riscv/insns/flwsegst_v.h b/riscv/insns/movz.h
similarity index 100%
rename from riscv/insns/flwsegst_v.h
rename to riscv/insns/movz.h
diff --git a/riscv/insns/fld_v.h b/riscv/insns/vfld.h
similarity index 100%
rename from riscv/insns/fld_v.h
rename to riscv/insns/vfld.h
diff --git a/riscv/insns/fsdseg_v.h b/riscv/insns/vflsegd.h
similarity index 100%
rename from riscv/insns/fsdseg_v.h
rename to riscv/insns/vflsegd.h
diff --git a/riscv/insns/fsdsegst_v.h b/riscv/insns/vflsegstd.h
similarity index 100%
rename from riscv/insns/fsdsegst_v.h
rename to riscv/insns/vflsegstd.h
diff --git a/riscv/insns/fswseg_v.h b/riscv/insns/vflsegstw.h
similarity index 100%
rename from riscv/insns/fswseg_v.h
rename to riscv/insns/vflsegstw.h
diff --git a/riscv/insns/fswsegst_v.h b/riscv/insns/vflsegw.h
similarity index 100%
rename from riscv/insns/fswsegst_v.h
rename to riscv/insns/vflsegw.h
diff --git a/riscv/insns/fldst_v.h b/riscv/insns/vflstd.h
similarity index 100%
rename from riscv/insns/fldst_v.h
rename to riscv/insns/vflstd.h
diff --git a/riscv/insns/flwst_v.h b/riscv/insns/vflstw.h
similarity index 100%
rename from riscv/insns/flwst_v.h
rename to riscv/insns/vflstw.h
diff --git a/riscv/insns/flw_v.h b/riscv/insns/vflw.h
similarity index 100%
rename from riscv/insns/flw_v.h
rename to riscv/insns/vflw.h
diff --git a/riscv/insns/fmov_su.h b/riscv/insns/vfmst.h
similarity index 100%
rename from riscv/insns/fmov_su.h
rename to riscv/insns/vfmst.h
diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/vfmsv.h
similarity index 100%
rename from riscv/insns/fmov_sv.h
rename to riscv/insns/vfmsv.h
diff --git a/riscv/insns/fmov_us.h b/riscv/insns/vfmts.h
similarity index 100%
rename from riscv/insns/fmov_us.h
rename to riscv/insns/vfmts.h
diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/vfmvv.h
similarity index 100%
rename from riscv/insns/fmov_vv.h
rename to riscv/insns/vfmvv.h
diff --git a/riscv/insns/fsd_v.h b/riscv/insns/vfsd.h
similarity index 100%
rename from riscv/insns/fsd_v.h
rename to riscv/insns/vfsd.h
diff --git a/riscv/insns/lbseg_v.h b/riscv/insns/vfssegd.h
similarity index 100%
rename from riscv/insns/lbseg_v.h
rename to riscv/insns/vfssegd.h
diff --git a/riscv/insns/lbsegst_v.h b/riscv/insns/vfssegstd.h
similarity index 100%
rename from riscv/insns/lbsegst_v.h
rename to riscv/insns/vfssegstd.h
diff --git a/riscv/insns/lbuseg_v.h b/riscv/insns/vfssegstw.h
similarity index 100%
rename from riscv/insns/lbuseg_v.h
rename to riscv/insns/vfssegstw.h
diff --git a/riscv/insns/lbusegst_v.h b/riscv/insns/vfssegw.h
similarity index 100%
rename from riscv/insns/lbusegst_v.h
rename to riscv/insns/vfssegw.h
diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/vfsstd.h
similarity index 100%
rename from riscv/insns/fsdst_v.h
rename to riscv/insns/vfsstd.h
diff --git a/riscv/insns/fswst_v.h b/riscv/insns/vfsstw.h
similarity index 100%
rename from riscv/insns/fswst_v.h
rename to riscv/insns/vfsstw.h
diff --git a/riscv/insns/fsw_v.h b/riscv/insns/vfsw.h
similarity index 100%
rename from riscv/insns/fsw_v.h
rename to riscv/insns/vfsw.h
diff --git a/riscv/insns/lb_v.h b/riscv/insns/vlb.h
similarity index 100%
rename from riscv/insns/lb_v.h
rename to riscv/insns/vlb.h
diff --git a/riscv/insns/lbu_v.h b/riscv/insns/vlbu.h
similarity index 100%
rename from riscv/insns/lbu_v.h
rename to riscv/insns/vlbu.h
diff --git a/riscv/insns/ld_v.h b/riscv/insns/vld.h
similarity index 100%
rename from riscv/insns/ld_v.h
rename to riscv/insns/vld.h
diff --git a/riscv/insns/lh_v.h b/riscv/insns/vlh.h
similarity index 100%
rename from riscv/insns/lh_v.h
rename to riscv/insns/vlh.h
diff --git a/riscv/insns/lhu_v.h b/riscv/insns/vlhu.h
similarity index 100%
rename from riscv/insns/lhu_v.h
rename to riscv/insns/vlhu.h
diff --git a/riscv/insns/ldseg_v.h b/riscv/insns/vlsegb.h
similarity index 100%
rename from riscv/insns/ldseg_v.h
rename to riscv/insns/vlsegb.h
diff --git a/riscv/insns/ldsegst_v.h b/riscv/insns/vlsegbu.h
similarity index 100%
rename from riscv/insns/ldsegst_v.h
rename to riscv/insns/vlsegbu.h
diff --git a/riscv/insns/lhseg_v.h b/riscv/insns/vlsegd.h
similarity index 100%
rename from riscv/insns/lhseg_v.h
rename to riscv/insns/vlsegd.h
diff --git a/riscv/insns/lhsegst_v.h b/riscv/insns/vlsegh.h
similarity index 100%
rename from riscv/insns/lhsegst_v.h
rename to riscv/insns/vlsegh.h
diff --git a/riscv/insns/lhuseg_v.h b/riscv/insns/vlseghu.h
similarity index 100%
rename from riscv/insns/lhuseg_v.h
rename to riscv/insns/vlseghu.h
diff --git a/riscv/insns/lhusegst_v.h b/riscv/insns/vlsegstb.h
similarity index 100%
rename from riscv/insns/lhusegst_v.h
rename to riscv/insns/vlsegstb.h
diff --git a/riscv/insns/lwseg_v.h b/riscv/insns/vlsegstbu.h
similarity index 100%
rename from riscv/insns/lwseg_v.h
rename to riscv/insns/vlsegstbu.h
diff --git a/riscv/insns/lwsegst_v.h b/riscv/insns/vlsegstd.h
similarity index 100%
rename from riscv/insns/lwsegst_v.h
rename to riscv/insns/vlsegstd.h
diff --git a/riscv/insns/lwuseg_v.h b/riscv/insns/vlsegsth.h
similarity index 100%
rename from riscv/insns/lwuseg_v.h
rename to riscv/insns/vlsegsth.h
diff --git a/riscv/insns/lwusegst_v.h b/riscv/insns/vlsegsthu.h
similarity index 100%
rename from riscv/insns/lwusegst_v.h
rename to riscv/insns/vlsegsthu.h
diff --git a/riscv/insns/sbseg_v.h b/riscv/insns/vlsegstw.h
similarity index 100%
rename from riscv/insns/sbseg_v.h
rename to riscv/insns/vlsegstw.h
diff --git a/riscv/insns/sbsegst_v.h b/riscv/insns/vlsegstwu.h
similarity index 100%
rename from riscv/insns/sbsegst_v.h
rename to riscv/insns/vlsegstwu.h
diff --git a/riscv/insns/sdseg_v.h b/riscv/insns/vlsegw.h
similarity index 100%
rename from riscv/insns/sdseg_v.h
rename to riscv/insns/vlsegw.h
diff --git a/riscv/insns/sdsegst_v.h b/riscv/insns/vlsegwu.h
similarity index 100%
rename from riscv/insns/sdsegst_v.h
rename to riscv/insns/vlsegwu.h
diff --git a/riscv/insns/lbst_v.h b/riscv/insns/vlstb.h
similarity index 100%
rename from riscv/insns/lbst_v.h
rename to riscv/insns/vlstb.h
diff --git a/riscv/insns/lbust_v.h b/riscv/insns/vlstbu.h
similarity index 100%
rename from riscv/insns/lbust_v.h
rename to riscv/insns/vlstbu.h
diff --git a/riscv/insns/ldst_v.h b/riscv/insns/vlstd.h
similarity index 100%
rename from riscv/insns/ldst_v.h
rename to riscv/insns/vlstd.h
diff --git a/riscv/insns/lhst_v.h b/riscv/insns/vlsth.h
similarity index 100%
rename from riscv/insns/lhst_v.h
rename to riscv/insns/vlsth.h
diff --git a/riscv/insns/lhust_v.h b/riscv/insns/vlsthu.h
similarity index 100%
rename from riscv/insns/lhust_v.h
rename to riscv/insns/vlsthu.h
diff --git a/riscv/insns/lwst_v.h b/riscv/insns/vlstw.h
similarity index 100%
rename from riscv/insns/lwst_v.h
rename to riscv/insns/vlstw.h
diff --git a/riscv/insns/lwust_v.h b/riscv/insns/vlstwu.h
similarity index 100%
rename from riscv/insns/lwust_v.h
rename to riscv/insns/vlstwu.h
diff --git a/riscv/insns/lw_v.h b/riscv/insns/vlw.h
similarity index 100%
rename from riscv/insns/lw_v.h
rename to riscv/insns/vlw.h
diff --git a/riscv/insns/lwu_v.h b/riscv/insns/vlwu.h
similarity index 100%
rename from riscv/insns/lwu_v.h
rename to riscv/insns/vlwu.h
diff --git a/riscv/insns/mov_su.h b/riscv/insns/vmst.h
similarity index 100%
rename from riscv/insns/mov_su.h
rename to riscv/insns/vmst.h
diff --git a/riscv/insns/mov_sv.h b/riscv/insns/vmsv.h
similarity index 100%
rename from riscv/insns/mov_sv.h
rename to riscv/insns/vmsv.h
diff --git a/riscv/insns/mov_us.h b/riscv/insns/vmts.h
similarity index 100%
rename from riscv/insns/mov_us.h
rename to riscv/insns/vmts.h
diff --git a/riscv/insns/mov_vv.h b/riscv/insns/vmvv.h
similarity index 100%
rename from riscv/insns/mov_vv.h
rename to riscv/insns/vmvv.h
diff --git a/riscv/insns/sb_v.h b/riscv/insns/vsb.h
similarity index 100%
rename from riscv/insns/sb_v.h
rename to riscv/insns/vsb.h
diff --git a/riscv/insns/sd_v.h b/riscv/insns/vsd.h
similarity index 100%
rename from riscv/insns/sd_v.h
rename to riscv/insns/vsd.h
diff --git a/riscv/insns/setvl.h b/riscv/insns/vsetvl.h
similarity index 100%
rename from riscv/insns/setvl.h
rename to riscv/insns/vsetvl.h
diff --git a/riscv/insns/sh_v.h b/riscv/insns/vsh.h
similarity index 100%
rename from riscv/insns/sh_v.h
rename to riscv/insns/vsh.h
diff --git a/riscv/insns/shseg_v.h b/riscv/insns/vssegb.h
similarity index 100%
rename from riscv/insns/shseg_v.h
rename to riscv/insns/vssegb.h
diff --git a/riscv/insns/shsegst_v.h b/riscv/insns/vssegd.h
similarity index 100%
rename from riscv/insns/shsegst_v.h
rename to riscv/insns/vssegd.h
diff --git a/riscv/insns/swseg_v.h b/riscv/insns/vssegh.h
similarity index 100%
rename from riscv/insns/swseg_v.h
rename to riscv/insns/vssegh.h
diff --git a/riscv/insns/swsegst_v.h b/riscv/insns/vssegstb.h
similarity index 100%
rename from riscv/insns/swsegst_v.h
rename to riscv/insns/vssegstb.h
diff --git a/riscv/insns/vssegstd.h b/riscv/insns/vssegstd.h
new file mode 100644
index 0000000..e69de29
diff --git a/riscv/insns/vssegsth.h b/riscv/insns/vssegsth.h
new file mode 100644
index 0000000..e69de29
diff --git a/riscv/insns/vssegstw.h b/riscv/insns/vssegstw.h
new file mode 100644
index 0000000..e69de29
diff --git a/riscv/insns/vssegw.h b/riscv/insns/vssegw.h
new file mode 100644
index 0000000..e69de29
diff --git a/riscv/insns/sbst_v.h b/riscv/insns/vsstb.h
similarity index 100%
rename from riscv/insns/sbst_v.h
rename to riscv/insns/vsstb.h
diff --git a/riscv/insns/sdst_v.h b/riscv/insns/vsstd.h
similarity index 100%
rename from riscv/insns/sdst_v.h
rename to riscv/insns/vsstd.h
diff --git a/riscv/insns/shst_v.h b/riscv/insns/vssth.h
similarity index 100%
rename from riscv/insns/shst_v.h
rename to riscv/insns/vssth.h
diff --git a/riscv/insns/swst_v.h b/riscv/insns/vsstw.h
similarity index 100%
rename from riscv/insns/swst_v.h
rename to riscv/insns/vsstw.h
diff --git a/riscv/insns/sw_v.h b/riscv/insns/vsw.h
similarity index 100%
rename from riscv/insns/sw_v.h
rename to riscv/insns/vsw.h
diff --git a/riscv/insns/vtcfgivl.h b/riscv/insns/vtcfgivl.h
new file mode 100644
index 0000000..e69de29
diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vvcfgivl.h
similarity index 100%
rename from riscv/insns/vcfgivl.h
rename to riscv/insns/vvcfgivl.h
-- 
2.30.2