From 29e473ef85dc184cf7d4e00e2b589fd98a6941f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Apr 2021 23:43:36 +0100 Subject: [PATCH] get pre-coriolis2 verilator (wishbone) functional --- ls180/pre_pnr/run_iverilog_wb_ls180.sh | 2 +- ls180/pre_pnr/run_verilator_ls180.sh | 27 ++++++++++++++++++ ls180/pre_pnr/run_verilator_wb_ls180.sh | 2 +- ls180/pre_pnr/test.py | 15 +++++----- ls180/pre_pnr/testwb.py | 38 +++++++------------------ 5 files changed, 48 insertions(+), 36 deletions(-) create mode 100755 ls180/pre_pnr/run_verilator_ls180.sh diff --git a/ls180/pre_pnr/run_iverilog_wb_ls180.sh b/ls180/pre_pnr/run_iverilog_wb_ls180.sh index 6b4bd26..db24552 100755 --- a/ls180/pre_pnr/run_iverilog_wb_ls180.sh +++ b/ls180/pre_pnr/run_iverilog_wb_ls180.sh @@ -10,7 +10,7 @@ make \ SIM=icarus \ TOPLEVEL=ls180 \ COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \ - COCOTB_HDL_TIMEUNIT=10ps \ + COCOTB_HDL_TIMEUNIT=100ps \ TESTCASE="wishbone_basic" \ MODULE="testwb" \ SIM_BUILD=sim_build_iverilog_wb_ls180 diff --git a/ls180/pre_pnr/run_verilator_ls180.sh b/ls180/pre_pnr/run_verilator_ls180.sh new file mode 100755 index 0000000..e618edf --- /dev/null +++ b/ls180/pre_pnr/run_verilator_ls180.sh @@ -0,0 +1,27 @@ +#!/bin/sh + +# create dummy memory files +yes 0 | head -128 > mem_1.init +yes 0 | head -32 > mem_1.init +touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init + +# Only run test in reset state as running CPU takes too much time to simulate +make \ + SIM=verilator \ + TOPLEVEL=ls180 \ + COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \ + COCOTB_HDL_TIMEUNIT=100ps \ + TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset,idcode_run" \ + VERILATOR_TRACE="1" \ + NOTUSEDCOMPILE_ARGS="--unroll-count 256 \ + --output-split 5000 \ + --output-split-cfuncs 500 \ + --output-split-ctrace 500 \ + -Wno-fatal \ + -Wno-BLKANDNBLK \ + -Wno-WIDTH" \ + MODULE="test" \ + SIM_BUILD=sim_build_iverilator_ls180 + + + diff --git a/ls180/pre_pnr/run_verilator_wb_ls180.sh b/ls180/pre_pnr/run_verilator_wb_ls180.sh index c5d882b..05512bd 100755 --- a/ls180/pre_pnr/run_verilator_wb_ls180.sh +++ b/ls180/pre_pnr/run_verilator_wb_ls180.sh @@ -11,7 +11,7 @@ make \ TOPLEVEL=ls180 \ COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \ COCOTB_HDL_TIMEUNIT=100ps \ - TESTCASE="wishbone_basic" \ + TESTCASE="idcode_run,wishbone_basic" \ VERILATOR_TRACE="1" \ NOTUSEDCOMPILE_ARGS="--unroll-count 256 \ --output-split 5000 \ diff --git a/ls180/pre_pnr/test.py b/ls180/pre_pnr/test.py index cb1611c..9617edf 100644 --- a/ls180/pre_pnr/test.py +++ b/ls180/pre_pnr/test.py @@ -27,12 +27,12 @@ class DUTWrapper: ti = dut ti._discover_all() self.ti = ti - self.clk = ti.clk - self.rst = ti.rst - self.tck = ti.TAP_bus__tck - self.tms = ti.TAP_bus__tms - self.tdi = ti.TAP_bus__tdi - self.tdo = ti.TAP_bus__tdo + self.clk = dut.sys_clk + self.rst = dut.sys_rst + self.tck = dut.jtag_tck + self.tms = dut.jtag_tms + self.tdi = dut.jtag_tdi + self.tdo = dut.jtag_tdo def info(self, *args, **kwargs): return self.dut._log.info(*args, **kwargs) @@ -152,8 +152,9 @@ def setup_jtag(wrap, *, tck_period): if False: # Yield is never executed but it makes this function a generator yield Timer(0) + clk_steps = get_sim_steps(tck_period, "ns") return JTAG_Master(wrap.tck, wrap.tms, wrap.tdi, wrap.tdo, - clk_period=tck_period, + clk_period=clk_steps, ir_width=4) def execute_svf(wrap, *, jtag, svf_filename): diff --git a/ls180/pre_pnr/testwb.py b/ls180/pre_pnr/testwb.py index 098558e..18a30c5 100644 --- a/ls180/pre_pnr/testwb.py +++ b/ls180/pre_pnr/testwb.py @@ -22,11 +22,11 @@ class DUTWrapper: def __init__(self, dut): self.dut = dut try: - ls180 = dut.ls180 + ti = dut.test_issuer except AttributeError: - ls180 = dut - ls180._discover_all() - self.ls180 = ls180 + ti = dut + ti._discover_all() + self.ti = ti self.clk = dut.sys_clk self.rst = dut.sys_rst self.tck = dut.jtag_tck @@ -34,11 +34,6 @@ class DUTWrapper: self.tdi = dut.jtag_tdi self.tdo = dut.jtag_tdo - return - ls180.test_issuer._discover_all() - ls180.test_issuer.ti._discover_all() - ls180.test_issuer.ti.dbg._discover_all() - def info(self, *args, **kwargs): return self.dut._log.info(*args, **kwargs) @@ -140,16 +135,15 @@ def setup_sim(dut, *, info, clk_period, run): wrap = DUTWrapper(dut) wrap.info(info) - wrap.clk <= 0 - wrap.rst <= 1 - clk_steps = get_sim_steps(clk_period, "ns") cocotb.fork(Clock(wrap.clk, clk_steps).start()) + wrap.rst <= 1 + wrap.clk <= 0 if run: yield Timer(int(10.5*clk_steps)) wrap.rst <= 0 - yield Timer(int(3*clk_steps)) + yield Timer(int(5*clk_steps)) return wrap @@ -331,16 +325,6 @@ def wishbone_basic(dut): master = yield from setup_jtag(wrap, tck_period = tck_period) - #clk_steps = get_sim_steps(clk_period, "ns") - #yield Timer(int(4.5*clk_steps)) - #wrap.rst <= 0 - - #yield master.reset() - - #yield Timer(int(10.5*clk_steps)) - - #wrap.rst <= 0 - # Load the memory address yield master.load_ir(cmd_MEMADDRESS) dut._log.info("Loading address") @@ -372,7 +356,7 @@ def wishbone_basic(dut): dut._log.info(" input: {}".format(data_in.binstr)) yield master.shift_data(data_in) dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "000000000000000000000000000000" + assert master.result.binstr == "000000000000000000000000000011" # Do read and write yield master.load_ir(cmd_MEMREADWRITE) @@ -398,7 +382,7 @@ def wishbone_basic(dut): dut._log.info(" input: {}".format(data_in.binstr)) yield master.shift_data(data_in) dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "00000000000000000000000000010" + assert master.result.binstr == "000000000000000000000000000011" # Do read yield master.load_ir(cmd_MEMREAD) @@ -423,7 +407,7 @@ def wishbone_basic(dut): dut._log.info(" input: {}".format(data_in.binstr)) yield master.shift_data(data_in) dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "00000000000000000000000000010" + assert master.result.binstr == "000000000000000000000000000011" # Do read yield master.load_ir(cmd_MEMREAD) # MEMREAD @@ -440,7 +424,7 @@ def wishbone_basic(dut): dut._log.info(" output: {}".format(master.result.binstr)) assert master.result.binstr == "01010101" * 4 - dut._log.info("{!r}".format(wbmem)) + #dut._log.info("{!r}".format(wbmem)) # demo / debug how to get boundary scan names. run "python3 test.py" -- 2.30.2