From 29e4c8bd06acf718328c76ec5d6c11e3274b21d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 10:00:53 -0700 Subject: [PATCH] Clarify with 'only' --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index fd4d4beb5..56f428548 100644 --- a/README.md +++ b/README.md @@ -420,7 +420,7 @@ Verilog Attributes and non-standard features - The port attribute ``abc_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect its most significant bit. + onto a bus port will affect only its most significant bit. Non-standard or SystemVerilog features for formal verification -- 2.30.2