From 29e51f5e97fabc4fd55b14927bdb0e7edb2cb960 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 11 Oct 2019 21:49:11 +0200 Subject: [PATCH] interconnect/wishbone: fix Converter case when buses are identical --- litex/soc/interconnect/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index d32799b6..1fbdf975 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -486,7 +486,7 @@ class Converter(Module): upconverter = UpConverter(master, slave) self.submodules += upconverter else: - master.connect(slave) + self.comb += master.connect(slave) class Cache(Module): -- 2.30.2