From 29ee6dd867cefd7c71d71bc97169d69aa2907590 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 12:42:14 +0000 Subject: [PATCH] add blinky lights so we know FPGA is alive --- examples/soc.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/examples/soc.py b/examples/soc.py index 8e489e1..8b85648 100644 --- a/examples/soc.py +++ b/examples/soc.py @@ -26,6 +26,7 @@ from gram.modules import MT41K256M16 from gram.frontend.wishbone import gramWishbone from nmigen_boards.versa_ecp5 import VersaECP5Platform +from nmigen_boards.test.blinky import Blinky from uartbridge import UARTBridge from crg import ECPIX5CRG @@ -124,6 +125,9 @@ class DDR3SoC(SoC, Elaboratable): m.submodules.dramcore = self.dramcore m.submodules.drambone = self.drambone + # add blinky lights so we know FPGA is alive + m.submodules.blinky = Blinky() + # connect the arbiter (of wishbone masters) # to the decoder (addressing wishbone slaves) comb += self._arbiter.bus.connect(self._decoder.bus) -- 2.30.2