From 29f524db2a771ccc5781547bd1ef20528d367641 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 03:54:41 +0100 Subject: [PATCH] have to move SV CSRs into processor_t --- riscv/processor.h | 9 +++++++++ riscv/sv.cc | 7 ------- riscv/sv.h | 20 ++++++-------------- 3 files changed, 15 insertions(+), 21 deletions(-) diff --git a/riscv/processor.h b/riscv/processor.h index e2c63c8..1c89da0 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -10,6 +10,9 @@ #include #include #include "debug_rom_defines.h" +#ifdef SPIKE_SIMPLEV +#include "sv_decode.h" +#endif class processor_t; class mmu_t; @@ -126,6 +129,12 @@ struct state_t #ifdef SPIKE_SIMPLEV uint64_t vl; uint64_t mvl; + sv_reg_csr_entry sv_csrs[SV_CSR_SZ]; + sv_reg_entry sv_int_tb[NXPR]; + sv_reg_entry sv_fp_tb[NFPR]; + sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ]; + sv_pred_entry sv_pred_int_tb[NXPR]; + sv_pred_entry sv_pred_fp_tb[NFPR]; #endif uint32_t fflags; diff --git a/riscv/sv.cc b/riscv/sv.cc index 4acc9d2..b0453e2 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -1,13 +1,6 @@ #include "sv.h" #include "sv_decode.h" -sv_reg_csr_entry sv_csrs[SV_CSR_SZ]; -sv_reg_entry sv_int_tb[NXPR]; -sv_reg_entry sv_fp_tb[NFPR]; -sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ]; -sv_pred_entry sv_pred_int_tb[NXPR]; -sv_pred_entry sv_pred_fp_tb[NFPR]; - bool sv_check_reg(bool intreg, uint64_t reg) { sv_reg_entry *r; diff --git a/riscv/sv.h b/riscv/sv.h index 1911cad..ef4f755 100644 --- a/riscv/sv.h +++ b/riscv/sv.h @@ -18,9 +18,12 @@ typedef struct { unsigned int packed : 1; // Packed SIMD=1 } sv_reg_csr_entry; -#define SV_CSR_SZ 16 - -extern sv_reg_csr_entry sv_csrs[SV_CSR_SZ]; +// TODO: define separate SV CSRs for M-mode and S-Mode +// M-Mode and S-Mode will need a minimum of 2 for int-only +// platforms, and a minimum of 4 for int/fp. +// this to be able to use SV for contiguous register save/restore +// in around 2 instructions rather than massive blocks of 31 +#define SV_CSR_SZ 16 // TODO: only 4? for RV32? // this is the "unpacked" table, generated from the CAM above // there are 2 of them: one for FP, one for INT regs. @@ -36,11 +39,6 @@ typedef struct { unsigned int active : 1; // enabled=1, disabled=0 } sv_reg_entry; -// 32 entries: it's the size of the register table that needs to double -// (regidx=6 i.e. actual target register is indexed by 2^6) -extern sv_reg_entry sv_int_tb[NXPR]; -extern sv_reg_entry sv_fp_tb[NFPR]; - typedef struct { unsigned int type : 1; // 0=INT, 1=FP uint64_t regkey: 5; // 5 bits @@ -50,8 +48,6 @@ typedef struct { unsigned int active: 1; // enabled=1, disabled=0 } sv_pred_csr_entry; -extern sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ]; - typedef struct { uint64_t regkey: 5; // 5 bits unsigned int zero : 1; // zeroing=1, skipping=0 @@ -60,10 +56,6 @@ typedef struct { unsigned int active: 1; // enabled=1, disabled=0 } sv_pred_entry; -// 32 entries -extern sv_pred_entry sv_pred_int_tb[NXPR]; -extern sv_pred_entry sv_pred_fp_tb[NFPR]; - bool sv_check_reg(bool intreg, uint64_t reg); #endif -- 2.30.2