From 29fa60513187a8d6ba1ca005dacd900f939277b0 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Wed, 18 Oct 2023 12:46:16 +0100 Subject: [PATCH] add single demo sv.dsrd instruction --- openpower/sv/biginteger/analysis.mdwn | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 26365a836..c50457fb0 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -351,7 +351,10 @@ long as the bits of RC are in the right place. The really interesting bit is that when Vectorised, the upper bits (now in RS) *are* in the right bit-positions to be ORed into the second `dsrd` operation. This allows -us to create a chain `sv.dsrd`. +us to create a chain `sv.dsrd`, and a single instruction +replaces all four above: + + sv.dsrd *r8, *r24, t1, t0 For larger shift amounts beyond an element bitwidth standard register move operations may be used, or, if the shift amount is static, -- 2.30.2