From 2a1b08aeb34b7d5f2df1a43c9ef1f99abacb9cae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 19:37:12 +0200 Subject: [PATCH] Added design->scratchpad --- kernel/rtlil.cc | 61 +++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 11 +++++++ passes/opt/opt.cc | 11 +++---- passes/opt/opt_clean.cc | 7 ++--- passes/opt/opt_const.cc | 20 ++----------- passes/opt/opt_muxtree.cc | 4 +-- passes/opt/opt_reduce.cc | 6 ++-- passes/opt/opt_rmdff.cc | 5 ++-- passes/opt/opt_share.cc | 4 +-- passes/opt/opt_status.h | 26 ----------------- 10 files changed, 91 insertions(+), 64 deletions(-) delete mode 100644 passes/opt/opt_status.h diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 96b651d89..72eced914 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -273,6 +273,67 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) return module; } +void RTLIL::Design::scratchpad_unset(std::string varname) +{ + scratchpad.erase(varname); +} + +void RTLIL::Design::scratchpad_set_int(std::string varname, int value) +{ + scratchpad[varname] = stringf("%d", value); +} + +void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value) +{ + scratchpad[varname] = value ? "true" : "false"; +} + +void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value) +{ + scratchpad[varname] = value; +} + +int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const +{ + if (scratchpad.count(varname) == 0) + return default_value; + + std::string str = scratchpad.at(varname); + + if (str == "0" || str == "false") + return 0; + + if (str == "1" || str == "true") + return 1; + + char *endptr = nullptr; + long int parsed_value = strtol(str.c_str(), &endptr, 10); + return *endptr ? default_value : parsed_value; +} + +bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const +{ + if (scratchpad.count(varname) == 0) + return default_value; + + std::string str = scratchpad.at(varname); + + if (str == "0" || str == "false") + return false; + + if (str == "1" || str == "true") + return true; + + return default_value; +} + +std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const +{ + if (scratchpad.count(varname) == 0) + return default_value; + return scratchpad.at(varname); +} + void RTLIL::Design::remove(RTLIL::Module *module) { for (auto mon : monitors) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d58873570..e35c3c681 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -486,6 +486,7 @@ struct RTLIL::Monitor struct RTLIL::Design { std::set monitors; + std::map scratchpad; int refcount_modules_; std::map modules_; @@ -508,6 +509,16 @@ struct RTLIL::Design RTLIL::Module *addModule(RTLIL::IdString name); void remove(RTLIL::Module *module); + void scratchpad_unset(std::string varname); + + void scratchpad_set_int(std::string varname, int value); + void scratchpad_set_bool(std::string varname, bool value); + void scratchpad_set_string(std::string varname, std::string value); + + int scratchpad_get_int(std::string varname, int default_value = 0) const; + bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + void check(); void optimize(); diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index b6d36f0e3..b20521d1e 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -17,14 +17,11 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/log.h" #include #include -bool OPT_DID_SOMETHING; - struct OptPass : public Pass { OptPass() : Pass("opt", "perform simple optimizations") { } virtual void help() @@ -113,9 +110,9 @@ struct OptPass : public Pass { while (1) { Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_share"); - OPT_DID_SOMETHING = false; + design->scratchpad_unset("opt.did_something"); Pass::call(design, "opt_rmdff"); - if (OPT_DID_SOMETHING == false) + if (design->scratchpad_get_bool("opt.did_something") == false) break; Pass::call(design, "opt_clean" + opt_clean_args); log_header("Rerunning OPT passes. (Removed registers in this run.)\n"); @@ -127,14 +124,14 @@ struct OptPass : public Pass { Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_share -nomux"); while (1) { - OPT_DID_SOMETHING = false; + design->scratchpad_unset("opt.did_something"); Pass::call(design, "opt_muxtree"); Pass::call(design, "opt_reduce" + opt_reduce_args); Pass::call(design, "opt_share"); Pass::call(design, "opt_rmdff"); Pass::call(design, "opt_clean" + opt_clean_args); Pass::call(design, "opt_const" + opt_const_args); - if (OPT_DID_SOMETHING == false) + if (design->scratchpad_get_bool("opt.did_something") == false) break; log_header("Rerunning OPT passes. (Maybe there is more to do..)\n"); } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index d47e4513e..cc4fe4cc8 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -88,7 +87,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto cell : unused) { if (verbose) log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); - OPT_DID_SOMETHING = true; + module->design->scratchpad_set_bool("opt.did_something", true); module->remove(cell); count_rm_cells++; } @@ -406,9 +405,9 @@ struct CleanPass : public Pass { for (auto &mod_it : design->modules_) { if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0) do { - OPT_DID_SOMETHING = false; + design->scratchpad_unset("opt.did_something"); rmunused_module(mod_it.second, purge_mode, false); - } while (OPT_DID_SOMETHING); + } while (design->scratchpad_get_bool("opt.did_something")); } if (count_rm_cells > 0 || count_rm_wires > 0) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a602cf5fd..ad6961872 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" @@ -67,7 +66,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); - OPT_DID_SOMETHING = true; + did_something = true; } } @@ -83,7 +82,6 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell assign_map.add(Y, out_val); module->connect(Y, out_val); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; } @@ -186,7 +184,6 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; return true; } @@ -266,7 +263,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; - OPT_DID_SOMETHING = true; did_something = true; } } @@ -293,7 +289,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; - OPT_DID_SOMETHING = true; did_something = true; } } @@ -320,7 +315,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort("\\B", sig_b = new_b); cell->parameters.at("\\B_WIDTH") = 1; - OPT_DID_SOMETHING = true; did_something = true; } } @@ -385,7 +379,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S")))); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -551,7 +544,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->unsetPort("\\B"); - OPT_DID_SOMETHING = true; did_something = true; } goto next_cell; @@ -588,7 +580,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo module->connect(cell->getPort("\\Y"), sig_y); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -661,7 +652,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.erase("\\B_SIGNED"); cell->check(); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -689,7 +679,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$not"; } else cell->type = "$_NOT_"; - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -709,7 +698,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$and"; } else cell->type = "$_AND_"; - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -729,7 +717,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$or"; } else cell->type = "$_OR_"; - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -781,7 +768,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); } - OPT_DID_SOMETHING = true; did_something = true; } } @@ -895,7 +881,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -928,7 +913,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->setPort("\\B", new_b); cell->check(); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -1018,6 +1002,8 @@ struct OptConstPass : public Pass { do { did_something = false; replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc); + if (did_something) + design->scratchpad_set_bool("opt.did_something", true); } while (did_something); replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc); } while (did_something); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index daa063812..2c5dcf668 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -179,7 +178,6 @@ struct OptMuxtreeWorker } else { log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(), mi.cell->type.c_str(), mi.cell->name.c_str()); - OPT_DID_SOMETHING = true; removed_count++; } } @@ -434,6 +432,8 @@ struct OptMuxtreePass : public Pass { total_count += worker.removed_count; } } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Removed %d multiplexer ports.\n", total_count); } } OptMuxtreePass; diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index e2b4243d1..e9e2bb399 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -88,7 +87,6 @@ struct OptReduceWorker if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; - OPT_DID_SOMETHING = true; total_count++; } @@ -141,7 +139,6 @@ struct OptReduceWorker if (new_sig_s.size() != sig_s.size()) { log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; - OPT_DID_SOMETHING = true; total_count++; } @@ -238,7 +235,6 @@ struct OptReduceWorker module->check(); did_something = true; - OPT_DID_SOMETHING = true; total_count++; } } @@ -376,6 +372,8 @@ struct OptReducePass : public Pass { } while (1); } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Performed a total of %d changes.\n", total_count); } } OptReducePass; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index bbf94d3b4..48f406f65 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -142,7 +141,6 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) delete_dff: log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str()); - OPT_DID_SOMETHING = true; mod->remove(dff); return true; } @@ -210,6 +208,9 @@ struct OptRmdffPass : public Pass { assign_map.clear(); mux_drivers.clear(); + + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Replaced %d DFF cells.\n", total_count); } } OptRmdffPass; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index e9a5e7fde..66f5e630c 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -265,7 +264,6 @@ struct OptShareWorker } log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); module->remove(cell); - OPT_DID_SOMETHING = true; total_count++; } else { sharemap[cell] = cell; @@ -315,6 +313,8 @@ struct OptSharePass : public Pass { total_count += worker.total_count; } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Removed a total of %d cells.\n", total_count); } } OptSharePass; diff --git a/passes/opt/opt_status.h b/passes/opt/opt_status.h deleted file mode 100644 index 3d12baa7d..000000000 --- a/passes/opt/opt_status.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef OPT_STATUS_H -#define OPT_STATUS_H - -extern bool OPT_DID_SOMETHING; - -#endif - -- 2.30.2