From 2a26aed6ad28a8261f5e2d8cfd3f8ae7355be934 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 14 Feb 2019 17:17:20 +0000 Subject: [PATCH] Arm: Add HF modes to ANY iterators The iterator ANY64 are used in various general split patterns and is supposed to contain all 64 bit modes. For some reason the pattern has HI but not HF. This adds HF so that general 64 bit splits are generated for these modes as well. These are required by various split patterns that expect them to be there. gcc/ChangeLog: PR target/88850 * config/arm/iterators.md (ANY64): Add V4HF. gcc/testsuite/ChangeLog: PR target/88850 * gcc.target/arm/pr88850-2.c: New test. * lib/target-supports.exp (check_effective_target_arm_neon_softfp_fp16_ok_nocache, check_effective_target_arm_neon_softfp_fp16_ok, add_options_for_arm_neon_softfp_fp16): New. From-SVN: r268884 --- gcc/ChangeLog | 5 +++ gcc/config/arm/iterators.md | 4 +-- gcc/testsuite/ChangeLog | 9 +++++ gcc/testsuite/gcc.target/arm/pr88850-2.c | 18 ++++++++++ gcc/testsuite/lib/target-supports.exp | 46 ++++++++++++++++++++++++ 5 files changed, 80 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/pr88850-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3da7175c627..727e37ee69f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-02-14 Tamar Christina + + PR target/88850 + * config/arm/iterators.md (ANY64): Add V4HF. + 2019-02-14 Martin Liska PR rtl-optimization/89242 diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index c33e572c3e8..eb07c5b90c1 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -24,9 +24,9 @@ ;;---------------------------------------------------------------------------- ;; A list of modes that are exactly 64 bits in size. This is used to expand -;; some splits that are the same for all modes when operating on ARM +;; some splits that are the same for all modes when operating on ARM ;; registers. -(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) +(define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF]) (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1d0a0fd5c49..4d2a2363183 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2019-02-14 Tamar Christina + + PR target/88850 + * gcc.target/arm/pr88850-2.c: New test. + * lib/target-supports.exp + (check_effective_target_arm_neon_softfp_fp16_ok_nocache, + check_effective_target_arm_neon_softfp_fp16_ok, + add_options_for_arm_neon_softfp_fp16): New. + 2019-02-14 Matthew Malcomson * gcc.dg/rtl/arm/ldrd-peepholes.c: Restrict testcase. diff --git a/gcc/testsuite/gcc.target/arm/pr88850-2.c b/gcc/testsuite/gcc.target/arm/pr88850-2.c new file mode 100644 index 00000000000..7a1aec55dc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr88850-2.c @@ -0,0 +1,18 @@ +/* PR target/88850. */ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -march=armv7-a -fdump-rtl-final" } */ +/* { dg-add-options arm_neon_softfp_fp16 } */ +/* { dg-require-effective-target arm_neon_softfp_fp16_ok } */ + +#include + +extern void c (int, float16x4_t); + +void a (float16x4_t b) +{ + c (0, b); +} + + +/* Check that these 64-bit moves are done in SI. */ +/* { dg-final { scan-rtl-dump "_movsi_vfp" "final" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 5e532555085..a56796393a5 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3785,6 +3785,44 @@ proc check_effective_target_arm_neon_fp16_ok { } { check_effective_target_arm_neon_fp16_ok_nocache] } +# Return 1 if this is an ARM target supporting -mfpu=neon-fp16 +# and -mfloat-abi=softfp together. Some multilibs may be +# incompatible with these options. Also set et_arm_neon_softfp_fp16_flags to +# the best options to add. + +proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } { + global et_arm_neon_softfp_fp16_flags + global et_arm_neon_flags + set et_arm_neon_softfp_fp16_flags "" + if { [check_effective_target_arm32] + && [check_effective_target_arm_neon_ok] } { + foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp" + "-mfloat-abi=softfp -mfp16-format=ieee" + "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} { + if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object { + #include "arm_neon.h" + float16x4_t + foo (float32x4_t arg) + { + return vcvt_f16_f32 (arg); + } + } "$et_arm_neon_flags $flags"] } { + set et_arm_neon_softfp_fp16_flags [concat $et_arm_neon_flags $flags] + return 1 + } + } + } + + return 0 +} + +proc check_effective_target_arm_neon_softfp_fp16_ok { } { + return [check_cached_effective_target arm_neon_softfp_fp16_ok \ + check_effective_target_arm_neon_softfp_fp16_ok_nocache] +} + + + proc check_effective_target_arm_neon_fp16_hw { } { if {! [check_effective_target_arm_neon_fp16_ok] } { return 0 @@ -3808,6 +3846,14 @@ proc add_options_for_arm_neon_fp16 { flags } { return "$flags $et_arm_neon_fp16_flags" } +proc add_options_for_arm_neon_softfp_fp16 { flags } { + if { ! [check_effective_target_arm_neon_softfp_fp16_ok] } { + return "$flags" + } + global et_arm_neon_softfp_fp16_flags + return "$flags $et_arm_neon_softfp_fp16_flags" +} + # Return 1 if this is an ARM target supporting the FP16 alternative # format. Some multilibs may be incompatible with the options needed. Also # set et_arm_neon_fp16_flags to the best options to add. -- 2.30.2