From 2a32925b047d05049f7038d04b3bcf294bc41d3c Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 17 Sep 2021 18:24:51 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index e42acf1a5..65a60429f 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -180,21 +180,9 @@ will rely. ## Data-dependent fail-first on CR operations (crand etc) Operations that actually produce or alter CR Field as a result -do not also in turn have an Rc=1 mode. However it makes no -sense to try to test the 4 bits of a CR Field for being equal -or not equal to zero. Moreover, the result is already in the -form that is desired: it is a CR field. Therefore, -CR-based operations have their own SVP64 Mode, described +have their own SVP64 Mode, described in [[sv/cr_ops]] -There are two primary different types of CR operations: - -* Those which have a 3-bit operand field (referring to a CR Field) -* Those which have a 5-bit operand (referring to a bit within the - whole 32-bit CR) - -More details can be found in [[sv/cr_ops]]. - # pred-result mode This mode merges common CR testing with predication, saving on instruction -- 2.30.2