From 2a35f3b52a6790173d3ceb086526b7b8dd15cd5d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Apr 2021 20:27:39 +0100
Subject: [PATCH] experiment with alternative PID in radix mmu

---
 src/soc/decoder/isa/radixmmu.py          |  7 ++---
 src/soc/decoder/isa/test_caller_radix.py | 33 ++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py
index e119932a..bd814457 100644
--- a/src/soc/decoder/isa/radixmmu.py
+++ b/src/soc/decoder/isa/radixmmu.py
@@ -415,8 +415,8 @@ class RADIX:
         print("_walk_tree")
         pidr  = self.caller.spr["PIDR"]
         prtbl = self.caller.spr["PRTBL"]
-        print(pidr)
-        print(prtbl)
+        print("PIDR", pidr)
+        print("PRTBL", prtbl)
         p = addr[55:63]
         print("last 8 bits ----------")
         print
@@ -671,9 +671,10 @@ class RADIX:
                 (effpid(31 downto 8) and finalmask(23 downto 0))) &
                 effpid(7 downto 0) & "0000";
         """
-        print ("_get_prtable_addr", shift, prtbl, addr, pid)
         finalmask = genmask(shift, 44)
         finalmask24 = finalmask[20:44]
+        print ("_get_prtable_addr", shift, prtbl, addr, pid,
+                bin(finalmask24.value))
         if addr[0].value == 1:
             effpid = SelectableInt(0, 32)
         else:
diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index c8b2f66d..26c813d0 100644
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -28,9 +28,20 @@ testmem = {
                         # R = 1 C = 1 ATT = 0 EAA 0x7
            0xc000000000000187,
 
+           0x30800:     # RADIX_ROOT_PTE + 8
+                        # V = 1 L = 0 NLB = 0x408 NLS = 9
+           0x8000000000040809,
+           0x40800:     # RADIX_SECOND_LEVEL
+                        # V = 1 L = 1 SW = 0 RPN = 0
+                        # R = 1 C = 1 ATT = 0 EAA 0x7
+           0xc000000000000187,
+
            0x1000000:   # PROCESS_TABLE_3
                         # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
            0x40000000000300ad,
+           0x1000008:   # PROCESS_TABLE_3 + 8
+                        # RTS1 = 0x2 RPDB = 0x308 RTS2 = 0x5 RPDS = 13
+           0x40000000000308ad,
           }
 
 prtbl = 0x1000000 # matches PROCESS_TABLE_3 above
@@ -59,6 +70,28 @@ class DecoderTestCase(FHDLTestCase):
                                                 initial_sprs=sprs)
             self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64))
 
+    def test_load_pid_1(self):
+        lst = [ "lwz 3, 0(1)"
+               ]
+        sprs = {'DSISR': SelectableInt(0, 64),
+                'DAR': SelectableInt(0, 64),
+                'PIDR': SelectableInt(1, 64),
+                'PRTBL': SelectableInt(prtbl, 64)
+        }
+
+        initial_regs=[0] * 32
+        initial_regs[1] = 0x1000
+        initial_regs[2] = 0x1234
+
+        initial_mem = deepcopy(testmem)
+        initial_mem[0x1000] = 0x1337 # data to be read
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_regs=initial_regs,
+                                                initial_mem=initial_mem,
+                                                initial_sprs=sprs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64))
+
     def test_load_store(self):
         lst = ["addi 1, 0, 0x1000",
                "addi 2, 0, 0x1234",
-- 
2.30.2