From 2a473d55487fcc833744eacf82451b40728fd283 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 May 2021 11:48:31 +0100
Subject: [PATCH] reduce nc pins by 5 for PLL

---
 libresoc/ls180.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index a03eef9..4b56d69 100644
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -155,11 +155,11 @@ def io():
     _io.append(make_uart("uart", 1))
 
     # not connected - eurgh have to adjust this to match the total pincount.
-    num_nc = 24
+    num_nc = 23
     num_nc += 4 # mspi1 comments out, litex problems 25mar2021
     num_nc += 6 # sd0 comments out, litex problems 25mar2021
     num_nc += 2 # pwm comments out, litex problems 25mar2021
-    num_nc += 4 # PLL disabled for now
+    #num_nc += 4 # PLL disabled for now
     nc = ' '.join("NC%d" % i for i in range(num_nc))
     _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
 
-- 
2.30.2