From 2a591f06bb01983912bd63fdf633ebb915b43da2 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 16 Jun 2020 12:17:47 +0200 Subject: [PATCH] Pulse trigger signal rather than continuous trigger in Timeline test --- gram/compat.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/gram/compat.py b/gram/compat.py index 05a5ade..9d183ef 100644 --- a/gram/compat.py +++ b/gram/compat.py @@ -134,6 +134,7 @@ class TimelineTestCase(unittest.TestCase): yield timeline.trigger.eq(1) yield + yield timeline.trigger.eq(0) for i in range(11+1): yield @@ -154,6 +155,12 @@ class TimelineTestCase(unittest.TestCase): self.assertFalse((yield sigA)) self.assertFalse((yield sigB)) + # Ensure no changes happen once the sequence is done + for i in range(100): + yield + self.assertFalse((yield sigA)) + self.assertFalse((yield sigB)) + sim = Simulator(m) with sim.write_vcd("test_compat.vcd"): sim.add_clock(1e-6) -- 2.30.2