From 2a6beaec38b4cef8ab292dfff768093b544c6723 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 15:07:47 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index c3e501252..2347ed6cf 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -180,8 +180,10 @@ Brief description of fields:
   destruction of LR during loops (particularly Vertical-First
   ones).
 * **VSb** In VLSET Mode, after testing,
-  if VSb is set, VL is truncated if the branch succeeds.  If VSb is clear,
-  VL is truncated if the branch did **not** take place.
+  if VSb is set, VL is truncated if the test succeeds.  If VSb is clear,
+  VL is truncated if a test *fails*. Masked-out (skipped)
+  bits are not considered
+  part of testing.
 * **CTi** CTR inversion. CTR-test Mode normally decrements per element
   tested. CTR inversion decrements if a test *fails*. Only relevant
   in CTR-test Mode.
-- 
2.30.2