From 2a71324d4934164ad8a697a55d765dc6cfec763e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Apr 2019 23:43:37 +0100 Subject: [PATCH] tidy up i_valid_logic --- src/add/singlepipe.py | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 2cb7d1ab..02b82352 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -195,15 +195,20 @@ class PrevControl: def i_valid_logic(self): vlen = len(self.i_valid) - if vlen > 1: # multi-bit case: valid only when i_valid is all 1s + if vlen > 1: + # multi-bit case: valid only when i_valid is all 1s all1s = Const(-1, (len(self.i_valid), False)) - if self.stage_ctl: - return self.i_valid == all1s & self.s_o_ready - return self.i_valid == all1s - # single-bit i_valid case + i_valid = (self.i_valid == all1s) + else: + # single-bit i_valid case + i_valid = self.i_valid + + # when stage indicates not ready, incoming data + # must "appear" to be not ready too if self.stage_ctl: - return self.i_valid & self.s_o_ready - return self.i_valid + i_valid = i_valid & self.s_o_ready + + return i_valid class NextControl: -- 2.30.2