From 2a77f2b21ff64b5f76a4812f5df8e32cda2c3eba Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 May 2020 12:43:30 +0100 Subject: [PATCH] swap encode responses, 3210 not 0123 for left mode --- src/soc/countzero/countzero.py | 10 +++++----- src/soc/countzero/test/test_countzero.py | 7 ++++++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/soc/countzero/countzero.py b/src/soc/countzero/countzero.py index 7826d947..bd61f571 100644 --- a/src/soc/countzero/countzero.py +++ b/src/soc/countzero/countzero.py @@ -53,14 +53,14 @@ class ZeroCounter(Elaboratable): with m.Else(): m.d.comb += ret.eq(3) with m.Else(): - with m.If(v[0]): - m.d.comb += ret.eq(0) - with m.Elif(v[1]): - m.d.comb += ret.eq(1) + with m.If(v[3]): + m.d.comb += ret.eq(3) with m.Elif(v[2]): m.d.comb += ret.eq(2) + with m.Elif(v[1]): + m.d.comb += ret.eq(1) with m.Else(): - m.d.comb += ret.eq(3) + m.d.comb += ret.eq(0) return ret r = IntermediateResult() diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py index e4ca3519..8bb3fe15 100644 --- a/src/soc/countzero/test/test_countzero.py +++ b/src/soc/countzero/test/test_countzero.py @@ -65,7 +65,7 @@ class ZeroCounterTestCase(FHDLTestCase): yield dut.count_right_i.eq(0) yield Delay(1e-6) result = yield dut.result_o - assert result == 8, "result %d" % result + assert result == 14, "result %d" % result yield dut.count_right_i.eq(1) yield Delay(1e-6) @@ -77,6 +77,11 @@ class ZeroCounterTestCase(FHDLTestCase): result = yield dut.result_o assert result == 23, "result %d" % result + yield dut.count_right_i.eq(0) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 14, "result %d" % result + sim.add_process(process) # or sim.add_sync_process(process), see below -- 2.30.2