From 2a818661e17027391770de91e0cc1e319c1053f2 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 1 Nov 2015 22:38:06 +0800
Subject: [PATCH] cores/dvi_sampler: fix imports

---
 misoc/cores/dvi_sampler/__init__.py    |  2 +-
 misoc/cores/dvi_sampler/analysis.py    |  5 ++---
 misoc/cores/dvi_sampler/chansync.py    | 12 +++++++-----
 misoc/cores/dvi_sampler/charsync.py    | 10 ++++++----
 misoc/cores/dvi_sampler/clocking.py    |  3 ++-
 misoc/cores/dvi_sampler/core.py        | 20 ++++++++++----------
 misoc/cores/dvi_sampler/datacapture.py |  3 ++-
 misoc/cores/dvi_sampler/debug.py       | 11 ++++++-----
 misoc/cores/dvi_sampler/decoding.py    |  2 +-
 misoc/cores/dvi_sampler/dma.py         | 10 ++++++----
 misoc/cores/dvi_sampler/edid.py        |  4 +++-
 misoc/cores/dvi_sampler/wer.py         | 12 +++++++-----
 12 files changed, 53 insertions(+), 41 deletions(-)

diff --git a/misoc/cores/dvi_sampler/__init__.py b/misoc/cores/dvi_sampler/__init__.py
index 073f8312..60f4b375 100644
--- a/misoc/cores/dvi_sampler/__init__.py
+++ b/misoc/cores/dvi_sampler/__init__.py
@@ -1 +1 @@
-from misoc.dvisampler.core import DVISampler
+from misoc.cores.dvi_sampler.core import DVISampler
diff --git a/misoc/cores/dvi_sampler/analysis.py b/misoc/cores/dvi_sampler/analysis.py
index 5f31a66f..d6084517 100644
--- a/misoc/cores/dvi_sampler/analysis.py
+++ b/misoc/cores/dvi_sampler/analysis.py
@@ -2,10 +2,9 @@ from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record
-from migen.bank.description import *
-from migen.flow.actor import *
 
-from misoc.dvisampler.common import channel_layout
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import channel_layout
 
 
 class SyncPolarity(Module):
diff --git a/misoc/cores/dvi_sampler/chansync.py b/misoc/cores/dvi_sampler/chansync.py
index ee416c39..093db3ec 100644
--- a/misoc/cores/dvi_sampler/chansync.py
+++ b/misoc/cores/dvi_sampler/chansync.py
@@ -1,11 +1,13 @@
+from functools import reduce
+from operator import or_, and_
+
 from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len
-from migen.genlib.misc import optree
-from migen.bank.description import *
 
-from misoc.dvisampler.common import channel_layout
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import channel_layout
 
 
 class _SyncBuffer(Module):
@@ -73,8 +75,8 @@ class ChanSync(Module, AutoCSR):
 
         some_control = Signal()
         self.comb += [
-            all_control.eq(optree("&", lst_control)),
-            some_control.eq(optree("|", lst_control))
+            all_control.eq(reduce(and_, lst_control)),
+            some_control.eq(reduce(or_, lst_control))
         ]
         self.sync.pix += If(~self.valid_i,
                 self.chan_synced.eq(0)
diff --git a/misoc/cores/dvi_sampler/charsync.py b/misoc/cores/dvi_sampler/charsync.py
index 266bb347..7912fb4b 100644
--- a/misoc/cores/dvi_sampler/charsync.py
+++ b/misoc/cores/dvi_sampler/charsync.py
@@ -1,9 +1,11 @@
+from functools import reduce
+from operator import or_
+
 from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import optree
-from migen.bank.description import *
 
-from misoc.dvisampler.common import control_tokens
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import control_tokens
 
 
 class CharSync(Module, AutoCSR):
@@ -26,7 +28,7 @@ class CharSync(Module, AutoCSR):
         control_position = Signal(max=10)
         self.sync.pix += found_control.eq(0)
         for i in range(10):
-            self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
+            self.sync.pix += If(reduce(or_, [raw[i:i+10] == t for t in control_tokens]),
                   found_control.eq(1),
                   control_position.eq(i)
             )
diff --git a/misoc/cores/dvi_sampler/clocking.py b/misoc/cores/dvi_sampler/clocking.py
index 0fc8969b..9c9c2ac0 100644
--- a/misoc/cores/dvi_sampler/clocking.py
+++ b/misoc/cores/dvi_sampler/clocking.py
@@ -1,6 +1,7 @@
 from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.bank.description import *
+
+from misoc.interconnect.csr import *
 
 
 class Clocking(Module, AutoCSR):
diff --git a/misoc/cores/dvi_sampler/core.py b/misoc/cores/dvi_sampler/core.py
index 545fbe89..f58e0d54 100644
--- a/misoc/cores/dvi_sampler/core.py
+++ b/misoc/cores/dvi_sampler/core.py
@@ -1,15 +1,15 @@
 from migen import *
-from migen.bank.description import AutoCSR
 
-from misoc.dvisampler.edid import EDID
-from misoc.dvisampler.clocking import Clocking
-from misoc.dvisampler.datacapture import DataCapture
-from misoc.dvisampler.charsync import CharSync
-from misoc.dvisampler.wer import WER
-from misoc.dvisampler.decoding import Decoding
-from misoc.dvisampler.chansync import ChanSync
-from misoc.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
-from misoc.dvisampler.dma import DMA
+from misoc.interconnect.csr import AutoCSR
+from misoc.cores.dvi_sampler.edid import EDID
+from misoc.cores.dvi_sampler.clocking import Clocking
+from misoc.cores.dvi_sampler.datacapture import DataCapture
+from misoc.cores.dvi_sampler.charsync import CharSync
+from misoc.cores.dvi_sampler.wer import WER
+from misoc.cores.dvi_sampler.decoding import Decoding
+from misoc.cores.dvi_sampler.chansync import ChanSync
+from misoc.cores.dvi_sampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
+from misoc.cores.dvi_sampler.dma import DMA
 
 
 class DVISampler(Module, AutoCSR):
diff --git a/misoc/cores/dvi_sampler/datacapture.py b/misoc/cores/dvi_sampler/datacapture.py
index 49f0ccef..c1de9efe 100644
--- a/misoc/cores/dvi_sampler/datacapture.py
+++ b/misoc/cores/dvi_sampler/datacapture.py
@@ -1,6 +1,7 @@
 from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
-from migen.bank.description import *
+
+from misoc.interconnect.csr import *
 
 
 class DataCapture(Module, AutoCSR):
diff --git a/misoc/cores/dvi_sampler/debug.py b/misoc/cores/dvi_sampler/debug.py
index 4121514f..f52a8b36 100644
--- a/misoc/cores/dvi_sampler/debug.py
+++ b/misoc/cores/dvi_sampler/debug.py
@@ -1,13 +1,14 @@
 from migen import *
 from migen.genlib.fifo import AsyncFIFO
-from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR
 from migen.actorlib import structuring, spi
 
-from misoc.mem.sdram.frontend import dma_lasmi
-from misoc.dvisampler.edid import EDID
-from misoc.dvisampler.clocking import Clocking
-from misoc.dvisampler.datacapture import DataCapture
+from misoc.cores.dvi_sampler.edid import EDID
+from misoc.cores.dvi_sampler.clocking import Clocking
+from misoc.cores.dvi_sampler.datacapture import DataCapture
+
+# TODO
+#from misoc.mem.sdram.frontend import dma_lasmi
 
 
 class RawDVISampler(Module, AutoCSR):
diff --git a/misoc/cores/dvi_sampler/decoding.py b/misoc/cores/dvi_sampler/decoding.py
index 6035c4c7..195fd33e 100644
--- a/misoc/cores/dvi_sampler/decoding.py
+++ b/misoc/cores/dvi_sampler/decoding.py
@@ -1,7 +1,7 @@
 from migen import *
 from migen.genlib.record import Record
 
-from misoc.dvisampler.common import control_tokens, channel_layout
+from misoc.cores.dvi_sampler.common import control_tokens, channel_layout
 
 
 class Decoding(Module):
diff --git a/misoc/cores/dvi_sampler/dma.py b/misoc/cores/dvi_sampler/dma.py
index 7ed4f829..8feab006 100644
--- a/misoc/cores/dvi_sampler/dma.py
+++ b/misoc/cores/dvi_sampler/dma.py
@@ -1,10 +1,12 @@
 from migen import *
 from migen.genlib.fsm import FSM, NextState
-from migen.bank.description import *
-from migen.bank.eventmanager import *
-from migen.flow.actor import *
 
-from misoc.mem.sdram.frontend import dma_lasmi
+from misoc.interconnect.csr import *
+from misoc.interconnect.csr_eventmanager import *
+
+# TODO: rewrite dma_lasmi module
+# TODO: use stream packets to resync DMA
+#from misoc.mem.sdram.frontend import dma_lasmi
 
 
 # Slot status: EMPTY=0 LOADED=1 PENDING=2
diff --git a/misoc/cores/dvi_sampler/edid.py b/misoc/cores/dvi_sampler/edid.py
index eb674b3e..a04e2361 100644
--- a/misoc/cores/dvi_sampler/edid.py
+++ b/misoc/cores/dvi_sampler/edid.py
@@ -3,7 +3,9 @@ from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import chooser
-from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
+
+from misoc.interconnect.csr import CSRStorage, CSRStatus, AutoCSR
+
 
 _default_edid = [
     0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
diff --git a/misoc/cores/dvi_sampler/wer.py b/misoc/cores/dvi_sampler/wer.py
index 904c225b..0bcd02ec 100644
--- a/misoc/cores/dvi_sampler/wer.py
+++ b/misoc/cores/dvi_sampler/wer.py
@@ -1,9 +1,11 @@
+from functools import reduce
+from operator import add, or_
+
 from migen import *
-from migen.bank.description import *
-from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoc.dvisampler.common import control_tokens
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import control_tokens
 
 
 class WER(Module, AutoCSR):
@@ -23,10 +25,10 @@ class WER(Module, AutoCSR):
         transitions = Signal(8)
         self.comb += [transitions[i].eq(data_r[i] ^ data_r[i+1]) for i in range(8)]
         transition_count = Signal(max=9)
-        self.sync.pix += transition_count.eq(optree("+", [transitions[i] for i in range(8)]))
+        self.sync.pix += transition_count.eq(reduce(add, [transitions[i] for i in range(8)]))
 
         is_control = Signal()
-        self.sync.pix += is_control.eq(optree("|", [data_r == ct for ct in control_tokens]))
+        self.sync.pix += is_control.eq(reduce(or_, [data_r == ct for ct in control_tokens]))
 
         # pipeline stage 3
         is_error = Signal()
-- 
2.30.2