From 2a82343319495a4219f1f460bfa4e609c047099a Mon Sep 17 00:00:00 2001 From: Jiong Wang Date: Wed, 8 Jun 2016 10:12:53 +0000 Subject: [PATCH] [AArch64, 3/6] Reimplement frsqrte intrinsics * config/aarch64/aarch64-builtins.def (rsqrte): New builtins for modes VALLF. * config/aarch64/aarch64-simd.md (aarch64_rsqrte_2): Rename to "aarch64_rsqrte". * config/aarch64/aarch64.c (get_rsqrte_type): Update gen* name. * config/aarch64/arm_neon.h (vrsqrts_f32): Remove inline assembly. Use builtin. (vrsqrted_f64): Likewise. (vrsqrte_f32): Likewise. (vrsqrte_f64): Likewise. (vrsqrteq_f32): Likewise. (vrsqrteq_f64): Likewise. From-SVN: r237202 --- gcc/ChangeLog | 15 +++ gcc/config/aarch64/aarch64-simd-builtins.def | 3 + gcc/config/aarch64/aarch64-simd.md | 2 +- gcc/config/aarch64/aarch64.c | 10 +- gcc/config/aarch64/arm_neon.h | 104 +++++++------------ 5 files changed, 62 insertions(+), 72 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9f6f3da351d..60d420a0cbc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2016-06-08 Jiong Wang + + * config/aarch64/aarch64-builtins.def (rsqrte): New builtins for modes + VALLF. + * config/aarch64/aarch64-simd.md (aarch64_rsqrte_2): Rename to + "aarch64_rsqrte". + * config/aarch64/aarch64.c (get_rsqrte_type): Update gen* name. + * config/aarch64/arm_neon.h (vrsqrts_f32): Remove inline assembly. Use + builtin. + (vrsqrted_f64): Likewise. + (vrsqrte_f32): Likewise. + (vrsqrte_f64): Likewise. + (vrsqrteq_f32): Likewise. + (vrsqrteq_f64): Likewise. + 2016-06-08 Jiong Wang * config/aarch64/aarch64-builtins.def (scvtf): Register vector modes. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index a7ea3c4b8ea..c26628699da 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -451,3 +451,6 @@ BUILTIN_VSDQ_SDI (BINOP_SUS, ucvtf, 3) BUILTIN_VALLF (BINOP, fcvtzs, 3) BUILTIN_VALLF (BINOP_USS, fcvtzu, 3) + + /* Implemented by aarch64_rsqrte. */ + BUILTIN_VALLF (UNOP, rsqrte, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index d2a6cc27de9..fc66a1676f8 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -382,7 +382,7 @@ [(set_attr "type" "neon_mul__scalar")] ) -(define_insn "aarch64_rsqrte_2" +(define_insn "aarch64_rsqrte" [(set (match_operand:VALLF 0 "register_operand" "=w") (unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")] UNSPEC_RSQRTE))] diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ad07fe196a8..acfb39dc025 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7349,11 +7349,11 @@ get_rsqrte_type (machine_mode mode) { switch (mode) { - case DFmode: return gen_aarch64_rsqrte_df2; - case SFmode: return gen_aarch64_rsqrte_sf2; - case V2DFmode: return gen_aarch64_rsqrte_v2df2; - case V2SFmode: return gen_aarch64_rsqrte_v2sf2; - case V4SFmode: return gen_aarch64_rsqrte_v4sf2; + case DFmode: return gen_aarch64_rsqrtedf; + case SFmode: return gen_aarch64_rsqrtesf; + case V2DFmode: return gen_aarch64_rsqrtev2df; + case V2SFmode: return gen_aarch64_rsqrtev2sf; + case V4SFmode: return gen_aarch64_rsqrtev4sf; default: gcc_unreachable (); } } diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 04bce9ab80c..e4f7a66abcc 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -9163,28 +9163,6 @@ vqrdmulhq_n_s32 (int32x4_t a, int32_t b) result; \ }) -__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -vrsqrte_f32 (float32x2_t a) -{ - float32x2_t result; - __asm__ ("frsqrte %0.2s,%1.2s" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - -__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -vrsqrte_f64 (float64x1_t a) -{ - float64x1_t result; - __asm__ ("frsqrte %d0,%d1" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vrsqrte_u32 (uint32x2_t a) { @@ -9196,39 +9174,6 @@ vrsqrte_u32 (uint32x2_t a) return result; } -__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -vrsqrted_f64 (float64_t a) -{ - float64_t result; - __asm__ ("frsqrte %d0,%d1" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - -__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrsqrteq_f32 (float32x4_t a) -{ - float32x4_t result; - __asm__ ("frsqrte %0.4s,%1.4s" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - -__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -vrsqrteq_f64 (float64x2_t a) -{ - float64x2_t result; - __asm__ ("frsqrte %0.2d,%1.2d" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vrsqrteq_u32 (uint32x4_t a) { @@ -9240,17 +9185,6 @@ vrsqrteq_u32 (uint32x4_t a) return result; } -__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -vrsqrtes_f32 (float32_t a) -{ - float32_t result; - __asm__ ("frsqrte %s0,%s1" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vrsqrts_f32 (float32x2_t a, float32x2_t b) { @@ -21504,6 +21438,44 @@ vrshrd_n_u64 (uint64_t __a, const int __b) return __builtin_aarch64_urshr_ndi_uus (__a, __b); } +/* vrsqrte. */ + +__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +vrsqrtes_f32 (float32_t __a) +{ + return __builtin_aarch64_rsqrtesf (__a); +} + +__extension__ static __inline float64_t __attribute__ ((__always_inline__)) +vrsqrted_f64 (float64_t __a) +{ + return __builtin_aarch64_rsqrtedf (__a); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrsqrte_f32 (float32x2_t __a) +{ + return __builtin_aarch64_rsqrtev2sf (__a); +} + +__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) +vrsqrte_f64 (float64x1_t __a) +{ + return (float64x1_t) {vrsqrted_f64 (vget_lane_f64 (__a, 0))}; +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrsqrteq_f32 (float32x4_t __a) +{ + return __builtin_aarch64_rsqrtev4sf (__a); +} + +__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +vrsqrteq_f64 (float64x2_t __a) +{ + return __builtin_aarch64_rsqrtev2df (__a); +} + /* vrsra */ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -- 2.30.2