From 2a873bccb508cac78ae97138c49eb79e297922d3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jun 2020 13:58:08 +0100 Subject: [PATCH] add handling of CA/CA32 in simulator, generated from sraw/srad --- src/soc/decoder/isa/caller.py | 10 +++++++--- src/soc/decoder/pseudo/parser.py | 4 +++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 6e1b895c..bb24035e 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -261,6 +261,7 @@ class ISACaller: self.namespace['XER'] = self.spr['XER'] self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value + self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value def handle_carry_(self, inputs, outputs): inv_a = yield self.dec2.e.invert_a @@ -278,7 +279,7 @@ class ISACaller: cy = 1 if any(gts) else 0 self.spr['XER'][XER_bits['CA']] = cy - + print ("inputs", inputs) # 32 bit carry gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1) for x in inputs] @@ -370,8 +371,11 @@ class ISACaller: for name, output in zip(output_names, results): if isinstance(output, int): output = SelectableInt(output, 256) - if name in info.special_regs: - print('writing special %s' % name, output) + if name in ['CA', 'CA32']: + print ("writing %s to XER" % name, output) + self.spr['XER'][XER_bits[name]].eq(output) + elif name in info.special_regs: + print('writing special %s' % name, output, special_sprs) if name in special_sprs: self.spr[name] = output else: diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py index 55db59cd..8b882f0c 100644 --- a/src/soc/decoder/pseudo/parser.py +++ b/src/soc/decoder/pseudo/parser.py @@ -611,7 +611,9 @@ class PowerParser: name = p[1] if name in self.available_op_fields: self.op_fields.add(name) - if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR', 'CA', 'CA32']: + if name in ['CA', 'CA32']: + self.write_regs.add(name) # add to list to write + if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR']: self.special_regs.add(name) self.write_regs.add(name) # and add to list to write p[0] = ast.Name(id=name, ctx=ast.Load()) -- 2.30.2