From 2ab16a277efb221702428b40a385c2e7adb63d59 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 9 Sep 2022 20:14:37 +0100 Subject: [PATCH] add fishmv fmvis addpcis instructions to test_pysvp64dis.py these are not hugely verbose --- src/openpower/sv/trans/test_pysvp64dis.py | 36 ++++++++++------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 2566d944..daec78c8 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -7,9 +7,7 @@ import sys class SVSTATETestCase(unittest.TestCase): - def test_0_addi(self): - expected = ['addi 1,5,2', - ] + def _do_tst(self, expected): isa = SVP64Asm(expected) lst = list(isa) with Program(lst, bigendian=False) as program: @@ -28,27 +26,25 @@ class SVSTATETestCase(unittest.TestCase): "instruction does not match " "'%s' expected '%s'" % (line, expected[i])) + + def test_0_addi(self): + expected = ['addi 1,5,2', + ] + self._do_tst(expected) + def test_1_svshape2(self): expected = [ 'svshape2 12,1,15,5,0,0' ] - isa = SVP64Asm(expected) - lst = list(isa) - with Program(lst, bigendian=False) as program: - print ("ops", program._instructions) - program.binfile.seek(0) - insns = load(program.binfile) - #for insn in insns: - #print ("insn", insn) - insns = list(insns) - print ("insns", insns) - for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)): - name = expected[i].split(" ")[0] - with self.subTest(name): - print("instruction", repr(line), repr(expected[i])) - self.assertEqual(expected[i], line, - "instruction does not match " - "'%s' expected '%s'" % (line, expected[i])) + self._do_tst(expected) + + def test_2_d_custom_op(self): + expected = [ + 'addpcis 12,5', + 'fishmv 12,2', + 'fmvis 12,97', + ] + self._do_tst(expected) if __name__ == "__main__": unittest.main() -- 2.30.2